Figure 18. Processor Reset# Signal Routing Topology With No Itp700Flex Connector; Figure 19. Processor Reset# Signal Routing Topology With Itp700Flex Connector - Intel 852GME Design Manual

R

Figure 18. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector

For a system that implements an ITP700FLEX debug port, a more elaborate topology is required in
order to guarantee proper signal quality at both the processor signal pad and the ITP700FLEX input
receiver. In this case the topology illustrated in Figure 19 should be implemented. The CPURESET#
signal from the GMCH should fork out (do not route one trace from GMCH pin and then T-split)
towards the processor's RESET# pin as well as towards the Rtt and Rs resistive termination network
placed next to the ITP700FLEX debug port connector. Rtt (54.9
and is placed at the end of the L2 line that is limited to a 12-inch maximum length. Rs (22.6
should be placed right next to Rtt to minimize the routing between them in the vicinity of the
ITP700FLEX connector to limit the L3 length to less than 0.5 inches. ITP700FLEX operation requires
the matching of L2 + L3 - L1 length to the length of the BPM[4:0]# signals length within ± 50 ps.
Currently 1% tolerance resistors are recommended for Rs and Rtt. The use of 5% tolerant resistors for
these resistors, and whether it could provide adequate signal quality performance, is under investigation.

Figure 19. Processor RESET# Signal Routing Topology with ITP700FLEX Connector

GMCH
56
CPU
CPURESET#
L2
® ®
Intel 852GME, Intel 852GMV and Intel
GMCH
L1
+ 1%) pulls-up to the VCCP voltage
VVC_CORE
Rtt
L4
L1
L3
Rs
®
852PM Chipset Platforms Design Guide
FSB Design Guidelines
± 1%)
CPU
RESET#
ITPFLEX
Connector
RESET#