A.2 Bus Interface; A.2.1 Updates To Descriptor Accessed And Tss Busy Bits; A.2.2 Locked And Unlocked Cmpxchg8B Operation - AMD K5 Technical Reference Manual

18524C/0—Nov1996
A.2 Bus Interface
A.2.1 Updates to Descriptor Accessed and TSS Busy Bits
A.2.2 Locked and Unlocked CMPXCHG8B Operation
Bus Interface
For updates to the Accessed bit in the data and code segment
descriptors, the behavior of the AMD-K5 processor is different
than the Pentium processor. In the aligned case, the AMD-K5
processor performs two 4-byte unlocked reads to read in the
descriptor. If the Accessed bit needs to be set, a 4-byte locked
read and a 4-byte locked write will follow. The Pentium proces-
sor performs an 8-byte unlocked read to get the descriptor. If
the Accessed bit needs to be set, an 8-byte locked read and a 1-
byte locked write will follow.
For the misaligned case, the AMD-K5 processor performs four
unlocked reads to get the descriptor. If the Accessed bit needs
to be set, two locked reads and two locked writes will follow.
The Pentium processor performs two unlocked reads to get the
descriptor. If the Accessed bit needs to be set, two locked
reads will be followed by one 1-byte locked write.
For updates to the Busy bit in the TSS descriptor, the AMD-K5
processor behaves in the manner described for updates to the
Accessed bit. The Pentium processor does not perform the
unlocked read to get the descriptor.
On a locked and misaligned— not on a dword boundary —
CMPXCHG8B operation, the AMD-K5 processor performs two
split reads followed by two split writes, all under lock, for a
total of eight cycles. The Pentium processor combines the split
reads and split writes, for a total of four cycles.
On a locked and aligned CMPXCHG8B operation, the AMD-K5
processor performs two 32-bit locked reads followed by two 32-
bit locked writes, all with SCYC asserted. The Pentium proces-
sor combines these 32-bit reads and writes into one 64-bit read
and one 64-bit write for the quadword-aligned case. The Pen-
tium processor performs the same operations at the AMD-K5
processor for the dword-aligned but quadword-misaligned
case.
AMD-K5 Processor Technical Reference Manual
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