Section 2 Preparations
● Event Inputs
A
B
C
D
E
1
2
3
4
5
6
2-10
Input control signals. The configuration is shown below.
D1
TIMING
D2
S-TMR
D3
HOLD
D4
RESET
D5
ZERO
D6
COM
Models with terminal blocks
<K35-1><K35-3>
Circuit Diagrams
<K35-1><K35-2> NPN Input Models
BANK (1,2,4)
S-TMR: D2
HOLD: D3
RESET: D4
ZERO: D5
COM
TIMING
COM
<K35-3><K35-4> PNP Input Models
BANK (1,2,4)
S-TMR: D2
HOLD: D3
RESET: D4
ZERO: D5
COM
TIMING
COM
1: TIMING
1
3: HOLD
5: ZERO
7: BANK4
9: BANK1
9
Models with connectors
<K35-2><K35-4>
Applicable connector:
XG4M-1030 (OMRON)
12 V
4.7 K
3.9 K
12 V
560
D1
750
3.9 K
4.7 K
12 V
750
D1
560
12 V
2: S-TMR
2
4: RESET
6: COM
8: BANK2
10
10: COM