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®
®
LV Intel
Pentium
III Processor 512K Dual Processor Platform
routing between component pins. Minimize the distance that traces have to be close and
parallel to each other, and maximize the distance between the sections when the spacing
restrictions relax.
•
Avoid parallelism between signals on adjacent layers if there is no AC reference plane
between them. As a rule of thumb, route adjacent layers orthogonally.
•
Since AGTL is a low signal swing technology, it is important to isolate AGTL signals from
other signals by at least 25 mils. This will avoid coupling from signals that have larger voltage
swings, such as 3.3 V system memory.
•
Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the
nominal characteristic impedance within the AGTL specification. This can be done by
minimizing the height of the trace from its reference plane, which minimizes the crosstalk.
•
Route AGTL address, data and control signals in separate groups to minimize crosstalk
between groups. Keep at least 25 mils between each group of signals.
•
Minimize the dielectric used in the system. This places the traces closer to their reference
plane and reduces the crosstalk magnitude.
•
Minimize the dielectric process variation used in the PCB fabrication.
•
Minimize the cross sectional area of the traces. This can be done by using narrower traces or
by using thinner copper, but the trade-off for this smaller cross sectional area is a higher trace
resistivity that can reduce the falling edge noise margin because of the I*R loss along the trace.
3.7
Layout Rules for Non-AGTL (CMOS) Signals
The following layout rules should be used for all CMOS signals:
The trace impedance should be 55 Ω +/- 10%.
•
•
External termination resistors should be placed in the middle of the trace to prevent long
reflection times and reduce reflection ledges.
•
Do not route CMOS traces next to AGTL traces. Switching noise on the AGTL traces may
attack the nearby CMOS traces.
•
Route a CMOS trace on one signal layer. If layer switching is unavoidable, minimize the
number of layer switches.
•
Try to use only one reference plane for a trace (either Vcc or Vss).
•
Although CMOS signals are slow, they may still have speed path problems. This is especially
true for APIC clock and APIC data. Try to avoid long routes.
3.8
Undershoot/Overshoot Requirements
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the
fast signal edge rates. The processor can be damaged by repeated overshoot events on buffers if the
charge is large enough (i.e., if the overshoot is great enough). Determining the impact of an
overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction and the
activity factor (AF). Permanent damage to the processor is the likely result of excessive
overshoot/undershoot. Violating the overshoot/undershoot guideline makes satisfying the ringback
specification difficult.
18
Design Guide
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