Cmos And Open Drain Signals; Signal Characteristics; Signal Reference Voltages - Intel E6420 - Core 2 Duo Dual-Core Processor Datasheet

.
Table 10.

Signal Characteristics

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, FCx
NOTES:
1. Signals that do not have R
.
Table 11.

Signal Reference Voltages

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
NOTES:
1. These signals also have hysteresis added to the reference voltage. See
information.
2.7.2

CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-
asserted for at least four BCLKs in order for the processor to recognize the proper
signal state. See
requirements for entering and leaving the low power states.
28
Signals with R
TT
1
Open Drain Signals
, nor are actively driven to their high-voltage level.
TT
GTLREF
Section 2.7.3 for the DC. See
Electrical Specifications
Signals with No R
A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#, TESTHI[13:0],
VID[6:1], GTLREF[1:0], TCK, TDI, TMS,
TRST#, VTT_SEL, MSID[1:0]
V /2
TT
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
1
PWRGOOD , SMI#, STPCLK#, TCK
1 1 1
TDI , TMS , TRST#
Table 13
Section 6.2 for additional timing
TT
1
,
for more
Datasheet