System Overview; Intel ® Pentium ® M Processor - Intel Pentium M Processor Design Manual

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Intel Pentium M Processor and Intel
Introduction
Table 2. Conventions and Terminology (Sheet 4 of 4)
Terminology
Intel P64H2
Hub Interface (HI)
In Target Probe (ITP)
1.3

System Overview

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The Intel
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Pentium
Cache. The chipset architecture provides the performance and feature-set required for uni-
processor based servers in the entry-level and mid-range, front-end, and general-purpose server and
embedded market segments. A chipset component interconnect, the Hub Interface 2.0 (HI2.0), is
designed into the Intel
components for high-speed I/O. Each HI2.0 provides 1.066 Gbytes/s I/O peak bandwidth. The
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Intel E7501 MCH has three HI2.0 connections, delivering 3.2 Gbytes/s peak bandwidth for high-
speed I/O, which may be used for PCI/PCI-X bridges. The system bus is used to connect the
processor with the Intel
400 MHz transfer rate for data transfers, delivering 3.2 Gbytes/s. The Intel
architecture supports a 144-bit wide, 200 MHz DDR memory interface also capable of transferring
data at 3.2 Gbytes/s.
In addition to these performance features, Intel
RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features required
for entry-level and mid-range servers. These features include: Intel
Correction (x4 SDDC) technology ECC for memory, ECC for all high-performance I/O,
out-of-band manageability through SMBus target interfaces on all chipset components, memory
scrubbing and auto-initialization, processor thermal monitoring, and Hot-Plug PCI. For a complete
list of the features on this platform, refer to the component datasheets listed in
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1.3.1 Intel
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The Intel
micro-architectural enhancements over existing Intel mobile processors. Some key features of the
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Intel Pentium
400-MHz source-synchronous Intel
level (L2) cache with Advanced Transfer Cache Architecture, Streaming SIMD Extensions 2
(SSE2), and Enhanced Intel
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The Intel
data to improve performance and enables addressing at 2X the system bus frequency and data
transfers at 4X the system bus frequency of 100 MHz. This allows the 400 MHz system bus
support to transfer data at 3.2 Gbytes/s.
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The Intel
architecture features described in the following sections:
24
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E7501 Chipset Platform
A component of the Intel E7501 chipset, the Intel
Hub 2 Bus Controller.
Intel high speed proprietary hub interconnect, known as the Hub Interface (HI),
that interfaces the Intel E7501 chipset to the Intel
In Target Probe - A debug tool that is needed to debug BIOS, logic, signal
integrity, general software, and hardware issues involving CPUs, chipsets, SIOs,
PCI devices, and other hardware in a platform.
E7501 Chipset is Intel's server/embedded chipset validated for use with the Intel
M Processor and the Intel
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E7501 Chipset to provide more efficient communication between chipset
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E7501 Chipset. The Intel
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Pentium M Processor
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Pentium M Processor is a high performance, lower voltage processor with several
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M processor micro-architecture include Dynamic Execution, data pre-fetch logic,
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SpeedStep
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Pentium M Processor system bus uses a source-synchronous transfer of address and
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Pentium M Processor with 1-Mbyte L2 cache includes the advanced micro-
Description
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Pentium M Processor on the 90 nm process with 2-MB L2
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Pentium
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E7501 Chipset-based platforms also provide the
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Pentium M processor system bus, on-die 1-Mbyte second
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technology.
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82870P2 PCI / PCI-X 64-bit
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ICH3-S and Intel P64H2.
M Processor system bus uses a
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E7501 Chipset
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x4 Single Device Data
Table 1.
Design Guide
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