Mitsubishi Q00JCPU User Manual page 651

APPENDICES
Number Name Meaning
Remaining No.
of simultaneous
execution of
SD780 0 to 32
CC-Link
dedicated
instruction
SD781 Mask pattern of
to IMASK Mask pattern
SD793 instruction
SD794 PID limit setting
0: Limit set
to (for incomplete
1: Limit not set
SD795 derivative)
SD781 Mask pattern of
to IMASK Mask pattern
SD785 instruction
PID limit setting
0: With limit
SD794 (for inexact
1: Without limit
differential)
*9: This applies to the CPU of function version B or later.
*13: This applies to the CPU with serial No. of first 5 digits "05032" or later.
TableApp.24 Special register
Explanation
• Stores the remaining number of simultaneous execution of the CC-Link
dedicated instructions.
• Stores the mask patterns masked by the IMASK instruction as follows:
b15
SD781 l63 to
l79
SD782 to
to
SD793 l255 to
• Specify the limit of each PID loop as shown below.
b15
SD794 Loop16 to
SD795 Loop32
to
• Stores the mask patterns masked by the IMASK instruction as follows:
b15
l63
SD781 to
SD782 l79 to
to to
l127
SD785 to
• Specify the limit of each PID loop as shown below.
b15 to b8 b7
Loop8
SD794
Set by
(When set)
U
b1 b0
l49 l48
S (During
l65 l64
execution)
l241 l240
b1 b0
U
Loop2 Loop1
Loop18 Loop17
b1 b0
l49
l48
S (During
l65 l64
execution)
l113 l112
b1 b0
U
Loop2 Loop1
to
Appendix 2 Special Register List
Corres-
ponding
Corresponding CPU
ACPU
D9
New QnA
Qn(H)
New QnPH
QnPRH
*13
Qn(H)
New
QnPRH
Q00J/Q00/Q01
New
*9
Q00J/Q00/Q01
App
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9
10
11