Mitsubishi Q00JCPU User Manual page 632

APPENDICES
Number Name Meaning
Error detection
SD54 MINI link errors
state
Number of
Number of module
SD60 module with
with blown fuse
blown fuse
I/O module I/O module
SD61 verification error verification error
number module number
Annunciator Annunciator
SD62
number number
Number of Number of
SD63
annunciators annunciators
SD64
SD65
SD66
SD67
SD68
SD69
SD70
SD71
Table of
detected Annunciator
SD72
annunciator detection number
numbers
SD73
SD74
SD75
SD76
SD77
SD78
SD79
SD80 CHK number CHK number
App
Appendix 2 Special Register List
- 37
TableApp.18 Special register
Explanation
1) When any of X(n+0)/X(n+20), X(n+6)/X(n+26), X(n+7)/X(n+27) and
X(n+8)/X(n+28) of the mounted MINI(-S3) turns ON, the bit of the
corresponding station turns to 1 (ON).
2) Turns to 1 (ON) when communication between the mounted MINI(-
S3) and CPU module cannot be made.
b15 to b9
8th 1st
module module
Information of 2)
• Value stored here is the lowest station I/O number of the module with
the blown fuse.
• The lowest I/O number of the module where the I/O module verification
number took place.
• The first annunciator number (F number) to be detected is stored here.
• Stores the number of annunciators searched.
OUT F
When F goes ON due to or
progressively ON from SD64 through SD79 are registered.
RST F
The F numbers turned OFF by
and the F numbers stored after the deleted F numbers are shifted to the
preceding registers.
LEDR
Execution of the instruction shifts the contents of SD64 to SD79
up by one.
(This can also be done by using the INDICATOR RESET switch on the of
the Q3A/Q4ACPU.)
After 16 annunciators have been detected, detection of the 17th will not be
stored from SD64 through SD79.
SET SET SET RST SET SET SET
F50 F25 F99 F25 F15 F70 F65
SD62 0 50 50 50 50 50 50 50 50 50 50 50 99 (Number
SD63 0 1 2 3 2 3 4 5
SD64 0 50 50 50 50 50 50 50 50 50 50 50 99
SD65 0 0 25 25 99 99 99 99 99 99 99 99 15
SD66 0 0 0 99 0 15 15 15 15 15 15 15 70
SD67 0 0 0 0 0 0 70 70 70 70 70 70 65
0 65 65 65 65 65 38
SD68 0 0 0 0 0 0
0 38 38 38 38 110
SD69 0 0 0 0 0 0 0
SD70 0 0 0 0 0 0 0 0
SD71 0 0 0 0 0 0 0 0
SD72 0 0 0 0 0 0 0 0
SD73 0 0 0 0 0 0 0 0
SD74 0 0 0 0 0 0 0 0
SD75 0 0 0 0 0 0 0 0
SD76 0 0 0 0 0 0 0 0
SD77 0 0 0 0 0 0 0 0
SD78 0 0 0 0 0 0 0 0
SD79 0 0 0 0 0 0 0 0
• Error codes detected by the CHK instruction are stored as BCD code.
b8 to b0
8th 1st
module module
Information of 1)
SET F
, the F numbers which go
are deleted from SD64 - SD79,
SET SET SET SET
F38 F110 F151 F210 LEDR
detected)
(Number of
6 7 8 9 8
annunciators
detected)
0 110 110 110 151
151 210
0 0 151 (Number
detected)
0 0 0 210 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
Corres-
ponding
Set by Corresponding
ACPU
(When set)
D9
D9004
S (Error) format
change
S (Error) D9000
S (Error) D9002
S (Instruction
D9009
execution)
S (Instruction
D9124
execution)
D9125
D9126
D9127
D9128
D9129
D9130
D9131
D9132
S (Instruction
New
execution)
New
New
New
New
New
New
New
S (Instruction
New
execution)
CPU
QnA
Rem
QnA
Qn(H)
QnPH
QnPRH