Kyocera KM-4230 Service Manual page 158

( 4 ) Reset circuit
CPU
IC7
V
CC
V
SH
V
SL
0.8 V DC
C
K
C
T
RES
Figure 2-3-16 CPU reset operation timing chart (abridged)
IC1 monitors the supply voltage and also determines if the CPU IC7 is operating
correctly. If the supply voltage V
(RES) is output to the CPU IC7 (A in the timing chart).
IC1 monitors the clock signal (CK) from pin 50 of the CPU IC7 which goes low
periodically. If the CPU IC7 fails, IC1 detects that the clock signal (CK) has stopped and
sends a reset signal (RES) to the CPU IC7 (B in the timing chart). To reset the CPU
IC7, pin 8 (RES) of IC1, which usually outputs 5 V DC, goes low and takes the level at
pin 7 of the CPU IC7 low.
+5 V DC
R1
50
7
1
C1
2
GROUND
Figure 2-3-15 Reset circuit
T
CK
drops below V
CC
+5 V DC
IC1
1
R2
2
RES
3
CK
8
RES
1
CT
R23 2
1
6
VREF
VS
1
+
C17
2
GROUND
B A
(approx. 4.2 V DC), the reset signal
SL
2
+5 V DC
5
Vcc
1
C7
2
4
GND
7
1
C2
2
2A3/4
2-3-19