Adsp-218X Dsp Core Architecture Overview - Analog Devices VisualDSP++ 3.5 Manual

ADSP-218x DSP Core Architecture Overview

Figure 2-6 shows the ADSP-218x DSP core architecture.
DATA ADDRESS
GENERATORS
PROGRAM
SEQUENCER
DAG1 DAG2
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
Figure 2-6. ADSP-218x DSP Functional Block Diagram
ADSP-218x DSPs use a modified Harvard architecture in which Data
Memory stores data and Program Memory stores both instructions and
data. All ADSP-218x processors contain on-chip RAM that comprises a
portion of the Program Memory space and Data Memory space. (Program
Memory and Data Memory are directly addressable off-chip.) The speed
of the on-chip memory allows the processor to fetch two operands (one
from Data Memory and one from Program Memory) and an instruction
(from Program Memory) in a single cycle. In each ADSP-218x processor,
five on-chip buses connect internal memory with the other functional
units. A single external address bus (14 bits) and a single external data bus
(24 bits) are extended off-chip; these buses can be used for either Program
or Data Memory accesses.
VisualDSP++ 3.5 Linker and Utilities Manual
for 16-Bit Processors
POWER-DOWN
CONTROL
MEMORY
PROGRAM DATA
MEMORY
MEMORY
UP TO
UP TO
48K 24-BIT 56K
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
SERIAL PORTS
SPORT0 SPORT1
PROGRAMMABLE
I/O
AND
FLAGS
16-BIT
TIMER
Linker
FULL MEMORY MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
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