Introduction To Memory Overlays - Analog Devices VisualDSP++ 3.5 Manual

Memory Overlays and Advanced LDF Commands
The following LDF commands facilitate overlay features.
• "OVERLAY_GROUP{}" on page 5-29
• "PLIT{}" on page 5-34

Introduction to Memory Overlays

When the built-in caching mechanisms are not used, memory overlays sup-
port applications that cannot fit the program instructions into the
processor's internal memory. In such cases, program instructions are parti-
tioned and stored in external memory until they are required for program
execution. These partitions are memory overlays, and the routines that call
and execute them are called overlay managers .
Overlays are a "many to one" memory mapping system. Several overlays
may "live" (stored) in unique locations in external memory, but "run"
(execute) in a common location in internal memory. Throughout the fol-
lowing description, the overlay storage location is referred to as the "live"
location, and the internal location where instructions are executed is
referred to as the "run" (run-time) space.
Overlay functions are written to overlay files (
fied as one type of linker executable output file. The loader can read
files to generate an .
done using the memory DMA controller.
Figure 5-1 demonstrates the concept of memory overlays. The two mem-
ory spaces are: internal and external. The external memory is partitioned
into five overlays. The internal memory contains the main program, an
overlay manager function, and two memory segments reserved for execu-
tion of overlay program instructions.
In this example, overlays 1 and 2 share the same run-time location within
internal memory, and overlays 3, 4, and 5 also share a common run-time
memory. When
VisualDSP++ 3.5 Linker and Utilities Manual
for 16-Bit Processors
file. On Blackfin processors, this function must be
LDR
is required, the overlay manager loads overlay 2 to
FUNC_B
), which may be speci-
.OVL
.OVL
5-5