Analog Devices VisualDSP++ 3.5 Manual page 216

Memory Management Using Overlays
Overlay live and run word sizes differ when internal memory and external
memory widths differ. A system containing 16-bit-wide external memory
requires data packing to store an overlay containing instructions.
L
The Blackfin processor architecture supports byte addressing that
uses 16-bit, 32-bit, or 64-bit opcodes. Thus, no data packing is
required.
Redirection. In addition to providing constants, the linker replaces over-
lay symbol references to the overlay manager within your code.
Redirection is accomplished by means of a procedure linkage table (PLIT).
A PLIT is essentially a jump table that executes user-defined code and
then jumps to the overlay manager. The linker replaces an overlay symbol
reference (function call) with a jump to a location in the PLIT.
You must define PLIT code within the
overlay manager to handle the overlay that contains the referenced sym-
bol. The code initializes registers to contain the overlay ID and the
referenced symbol's run-time address.
L
The linker reserves one word (or two bytes in Blackfin processors)
at the top of an overlay to house the overlay ID.
Listing 5-2 is an example PLIT definition from an
is set to the value of the overlay ID that contains the referenced symbol
R0
and register
R1
last instruction branches to the overlay manager that uses the initialized
registers to determine which overlay to load (and where to jump to exe-
cute the called overlay function).
Listing 5-2. PLIT Definition in LDF
PLIT
{
R0.l = PLIT_SYMBOL_OVERLAYID;
R1.h = PLIT_SYMBOL_ADDRESS;
R1.l = PLIT_SYMBOL_ADDRESS;
5-10
is set to the run-time address of the referenced symbol. The
VisualDSP++ 3.5 Linker and Utilities Manual
file. This code prepares the
.LDF
file, where register
.LDF
for 16-Bit Processors