Analog Devices VisualDSP++ 3.5 Manual page 49

4K SRAM
DCACHE/SRAM
L1 DATA MEMORY
CORE D0 BUS CORE D1 BUS
CORE L2 BUS SYS L2 BUS
256 KB L2 SRAM
32 KB
...
BLOCK 0
SRAM
MEMORY
Figure 2-5. ADSP-BF535 System Block Diagram
VisualDSP++ 3.5 Linker and Utilities Manual
for 16-Bit Processors
PROCESSOR
MEMORY
MANAGEMENT
UNIT
SYSTEM BUS INTERFACE UNIT (SBIU)
32 KB
BLOCK 7
SRAM
MEMORY
ASYNCHRONOUS
ICACHE/ SRAM
L1 INSTRUCTION MEMORY
CONTROL
PCI
EBIU
PCI MEMORY
AND I/O
AND
SYNCHRONOUS
MEMORY
Linker
SYSL1 BUS CORE I BUS
PERIPHERAL ACCESS BUS
(PAB)
DMA ACCESS BUS (DAB)
EXTERNAL ACCESS BUS
(EAB)
EXTERNAL MASTERED BUS
(EMB)
2-13