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Analog Devices VisualDSP++ 3.5 Manual

Analog Devices VisualDSP++ 3.5 Manual

Loader manual for 16-bit processors
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W 3.5
Loader Manual
for 16-Bit Processors
Revision 1.0, October 2003
Part Number
82-000035-04
Analog Devices, Inc.
One Technology Way
a
Norwood, Mass. 02062-9106

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  • Page 1 W 3.5 Loader Manual for 16-Bit Processors Revision 1.0, October 2003 Part Number 82-000035-04 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106...

  • Page 2: Copyright Information

    Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...

  • Page 3: Table Of Contents

    From VisualDSP++ .............. xvi From Windows ..............xvi From the Web ..............xvii Printed Manuals ..............xvii VisualDSP++ Documentation Set ........xvii Hardware Manuals ............. xviii Datasheets ................. xviii Contacting DSP Publications ..........xviii VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 4 ADSP-BF535 Processor Booting ..........2-3 ADSP-BF535 Processor On-Chip Boot ROM ..... 2-4 ADSP-BF535 Processor Second-Stage Loader ...... 2-6 ADSP-BF535 Processor Boot Streams ......... 2-8 Output Loader Files ............2-9 Global Headers and Blocks ........... 2-11 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 5 ADSP-BF531/BF532/BF533 and ADSP-BF561 Multiple .DXE Booting 2-37 Blackfin Processor Loader Guide ..........2-40 Using Loader Command Line ..........2-40 File Searches ..............2-41 File Extensions ..............2-41 Command-Line Switches ........... 2-42 Using Base Loader ..............2-47 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 6 No-booting ................3-12 Enriching Boot EPROMs with No-boot Data ....3-16 ADSP-219x DSP Loader Guide ..........3-19 ADSP-219x Loader Command-Line Reference ...... 3-19 File Searches ..............3-20 File Extensions ..............3-20 Loader Switches ..............3-21 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 7 ADSP-218x DSP Loader Guide ............. 5-1 Boot Modes ................5-2 Determining Boot Modes ............5-4 EPROM Booting (BDMA) ............5-6 ADSP-218x BDMA Loader Command-Line Reference ..5-7 File Searches ..............5-9 File Extensions ..............5-9 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 8 Linker Output Files ..............A-6 Memory Map Files ..............A-7 Loader Output Files in Intel Hex-32 Format ......A-7 Splitter Output Files in ASCII Format ........A-9 Debugger Files ................A-9 Format References ..............A-10 viii VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 9 Contents INDEX VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 10 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 11: Preface

    Thank you for purchasing Analog Devices development software for digital signal processor (DSP) applications. Purpose of This Manual The VisualDSP++ 3.5 Loader Manual for 16-Bit Processors contains infor- mation on how to use the loader/splitter to convert executable files into boot-loadable (or non-bootable) files for 16-bit fixed-point ADSP-21xx ®...

  • Page 12: Manual Contents

    • Email questions to dsptools.support@analog.com • Phone questions to 1-800-ANALOGD • Contact your ADI local sales office or authorized distributor • Send questions by mail to: Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 VisualDSP++ Loader Manual...

  • Page 13: Supported Processors

    ADSP-2188L/88N, and ADSP-2189M/89N • ADSP-219x family DSPs: ADSP-2191, ADSP-2192-12, ADSP-2195, ADSP-2196, ADSP-21990, ADSP-21991, and ADSP-21992 The name “Blackfin” refers to a family of Analog Devices 16-bit, embed- ded processors. VisualDSP++ currently supports the following Blackfin processors. • Blackfin Processors: ADSP-BF531, ADSP-BF532 (formerly...

  • Page 14: Myanalog.com

    Product Information MyAnalog.com MyAnalog.com is a free feature of the Analog Devices website that allows customization of a webpage to display only the latest information on products you are interested in. You can also choose to receive weekly email notification containing updates to the webpages that meet your interests.

  • Page 15: Related Documents

    VisualDSP++ 3.5 Linker and Utilities Manual for 16-Bit Processors VisualDSP++ 3.5 Assembler and Preprocessor Manual for Blackfin Processors VisualDSP++ 3.5 Assembler and Preprocessor Manual for ADSP-218x and ADSP-219x DSPs VisualDSP++ 3.5 Kernel (VDK) User’s Guide for 16-Bit Processors VisualDSP++ 3.5 Component Software Engineering User’s Guide for 16-Bit Processors Quick Installation Reference Card For hardware information, refer to your DSP’s Hardware Reference manual...

  • Page 16: From Visualdsp

    VisualDSP++ CD-ROM at any time by rerunning the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows Explorer, or Analog Devices Web site. From VisualDSP++ • Access VisualDSP++ online Help from the Help menu’s Contents, Search, and Index commands.

  • Page 17: From The Web

    .CHM Using the Windows Start Button Access VisualDSP++ online Help by clicking the Start button and choos- ing Programs, Analog Devices, VisualDSP++ for 16-bit processors , and VisualDSP++ Documentation. From the Web To download the tools manuals, point your browser at www.analog.com/technology/dsp/developmentTools/gen_purpose.html...

  • Page 18: Hardware Manuals

    Product Information If you do not have an account with Analog Devices, you will be referred to Analog Devices distributors. To get information on our distributors, log onto http://www.analog.com/salesdir/continent.asp Hardware Manuals Hardware reference and instruction set reference manuals can be ordered through the Literature Center or downloaded from the Analog Devices Web site.

  • Page 19: Notation Conventions

    Preface Notation Conventions The following table identifies and describes text conventions used in this manual. Additional conventions, which apply only to specific chapters, may appear throughout this document. Example Description Close command Text in bold style indicates the location of an item within the (File menu) VisualDSP++ environment’s menu system.
  • Page 20 Notation Conventions VisualDSP++ Loader Manual for 16-Bit Processors...

  • Page 21: Introduction

    “ADSP-218x DSP Loader/Splitter” on page 5-1 Program Development Flow The flow can be split into three phases: “Compiling and Assembling” “Linking” “Loading and Splitting” A brief description of each phase is as follows. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 22: Compiling And Assembling

    They are neither supposed to be burned onto a EPROM or Flash memory device. Executable files are consumed by VisualDSP++ debugging targets, such as the simulator or emulator. Refer to the VisualDSP++ 3.5 Linker and Utilities Manual for 16-Bit Processors and online Help for infor- mation about linking and debugging.
  • Page 23 • Use VisualDSP++ to simulate booting in a simulator session (where supported). Load the loader file and then reset the processor to debug the booting routines. No hardware is required: just point to VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 24: Boot-Loadable Files Versus Non-Bootable Files

    The splitter is invoked by a completely different set of command-line switches than the loader. Refer to the guide sections of the following chapters for information about splitting. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 25: Booting Modes

    EPROM/Flash memory devices directly. This scheme does not require any loader mechanism. It is up to the user program to initialize volatile memories. The splitter utility helps to generate a file that can be burned into the PROM memory. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 26: Prom Booting Mode

    The loader/splitter utility generates a file that can be consumed by the host device. It depends on the intelligence of the host device and on the target architecture whether the host expects raw application data or a for- matted boot stream. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 27: Boot Kernels

    The on-chip boot ROM for the former processors behaves similar to the second-stage loader of ADSP-BF535 pro- cessors. The boot ROM has the capability to parse address and count information for each bootable block. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 28: Loader Tasks

    Com- mon block types are “zero” (memory is filled with 0s); non-zero (code or data); and final (code or data). Depending on the processor family, there may be other block types. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 29: File Searches

    Place the files in the same directory as the executable file that refers to them. The loader can locate them when processing the executable. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 30 When providing an input or output file as a loader/splitter command-line parameter, use the following guidelines. • Enclose long file names within straight quotes, “long file name” • Append the appropriate file extension to each file. 1-10 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 31: Blackfin Processor Loader/Splitter

    2 BLACKFIN PROCESSOR LOADER/SPLITTER This chapter explains how the loader/splitter program ( ) is elfloader.exe used to convert executable files (. ) into boot-loadable or non-bootable files for the ADSP-BF5xx Blackfin processors. Refer to “Introduction” on page 1-1 for the loader overview; the introduc- tory material applies to all processor families.

  • Page 32: Blackfin Processor Booting

    Blackfin Processor Booting Blackfin Processor Booting Figure 2-1 is a simplified view of the Blackfin processor’s booting sequence. .ASM, .C, .CPP .DXE .DOJ Assembler Source Files Linker Loader and/or Compiler .LDR Target System Booting upon RESET External ADSP-BF53x Memory Processor Figure 2-1.

  • Page 33: Adsp-Bf535 Processor Booting

    Blackfin Processor Loader/Splitter Refer to the processor’s data sheet and Hardware Reference for more information on system configuration, peripherals, registers, and operating modes. ADSP-BF535 Processor Booting Upon reset, an ADSP-BF535 processor jumps to an external 16-bit mem- ory for execution (if ) or to the on-chip boot ROM (if BMODE = 000 Table 2-1...

  • Page 34: Adsp-Bf535 Processor On-Chip Boot Rom

    Blackfin Processor Booting ADSP-BF535 Processor On-Chip Boot ROM The on-chip boot ROM for the ADSP-BF535 processor does the follow- (Figure 2-2). ADSP-BF535 Processor 0xEF00 0000 On-Chip Boot ROM L2 Memory (0xF000 0000) 4-Byte Header (N) 2 nd Stage Loader 2 nd Stage Loader 2 nd Stage Loader Application Application...
  • Page 35 Blackfin Processor Loader/Splitter System Reset Configuration Register (SYSCR) X - state is initialized from mode pins during hardware reset 15 14 13 12 11 10 Reset = dependent on pin values No Boot on Software Reset BMODE 2-0 - RO 0 - Use BMODE to determine 000 - Bypass boot ROM, boot source.

  • Page 36: Adsp-Bf535 Processor Second-Stage Loader

    Blackfin Processor Booting ADSP-BF535 Processor Second-Stage Loader The only situation where a second-stage loader is unnecessary is when the application code contains only one section starting at the beginning of L2 memory ( 0xF000 0000 A second-stage loader must be used in applications in which multiple seg- ments reside in L2 memory or in L1 memory and/or SDRAM.
  • Page 37 Blackfin Processor Loader/Splitter 2. The second-stage loader copies itself to the bottom of L2 memory. ADSP-BF535 Processor 0xEF00 0000 On-Chip Boot ROM PROM/Flash or SPI Device L2 Memory 4-Byte Header (N) (0xF000 0000) 2 nd Stage Loader 2 nd Stage Loader 2 nd Stage Loader Application Code...

  • Page 38: Adsp-Bf535 Processor Boot Streams

    Blackfin Processor Booting 4. Finally, after booting, the second-stage loader jumps to the start of L2 memory ( ) for application code execution 0xF000 0000 (Figure 2-7). ADSP-BF535 Processor PROM/Flash or SPI Device 4-Byte Header (N) 0xEF00 0000 L2 Memory 2nd Stage Loader (0xF000 0000) On-Chip...

  • Page 39: Output Loader Files

    Blackfin Processor Loader/Splitter Diagrams in this section illustrate boot streams utilized by the ADSP-BF535 processor’s boot kernel. The elements are covered as follows. • “Output Loader Files” on page 2-9 • “Global Headers” on page 2-12 • “Block Headers” on page 2-13 •...
  • Page 40 Blackfin Processor Booting An output loader file for 16-bit PROM/Flash booting without the sec- ond-stage loader: Output .LDR File 4-Byte Header for Byte Count for 0x00 Byte Count (N) Stage Loader 0x00 Byte 0 0x00 Byte 1 Byte 2 0x00 Application 0x00 Code...

  • Page 41: Global Headers And Blocks

    Blackfin Processor Loader/Splitter An output loader file for 16-bit PROM/FLASH booting with the sec- ond-stage loader or kernel: Output .LDR File 4-Byte Header for Byte Count for 0x00 Byte Count (N) Stage Loader 0x00 Byte 0 0x00 Byte 1 Stage Loader 0x00 Byte 2 0x00...
  • Page 42 Blackfin Processor Booting A block is the basic structure of the output . file for application code when the second-stage loader is used. All the application code is grouped into blocks. A block always has a block header an a block body if it is a non-zero block.

  • Page 43: Flags

    Blackfin Processor Loader/Splitter Block Headers A block header has three words: 4-byte clock start address, 4-byte block byte count, and 2-byte flag word. Flags The ADSP-BF535 block flag word’s bits are illustrated below. 15 14 13 12 11 10 9 Bit 15: 1 = Last Block, 0 = Not Last Block Bit 0: 1 = Zero Fill, 0 = No Zero Fill ADSP-BF535 Processor Memory Ranges...

  • Page 44: Second-Stage Loader Restrictions

    Blackfin Processor Booting Bank 2 ( " 0x1000 0000 Bank 3 ( " 0x1800 0000 SDRAM must be initialized by user code before any instructions or data are loaded into it. For more information see “Using Second-Stage Loader” on page 2-49.
  • Page 45 Blackfin Processor Loader/Splitter The two reasons for this restriction are: • Core writes into L1 instruction memory are not allowed. • DMA from an 8-bit external memory is not possible since the minimum width of the External Bus Interface Unit (EBIU) is 16 bits.

  • Page 46: Adsp-Bf531/Bf532/Bf533 Processor Booting

    Blackfin Processor Booting ADSP-BF531/BF532/BF533 Processor Booting Upon reset, an ADSP-BF531/BF532/BF533 processor jumps to the on-chip boot ROM (if ) or jumps to 16-bit external mem- BMODE = 01 ory for execution (if ) located at Table 2-2 shows BMODE = 00 0xEF00 0000 booting modes and execution start addresses for ADSP-BF531, ADSP-BF532, and ADSP-BF533 processors.

  • Page 47: Adsp-Bf531/Bf532/Bf533 Processor On-Chip Boot Rom

    Blackfin Processor Loader/Splitter ADSP-BF531/BF532/BF533 Processor On-Chip Boot ROM The on-chip boot ROM for ADSP-BF531/BF532/BF533 processors does the following. 1. Sets up supervisor mode by exiting the interrupt service rou- RESET tine and jumping into the lowest priority interrupt ( IVG15 2.
  • Page 48 Blackfin Processor Booting ADSP-BF531/BF532/BF533 Processor PROM/Flash or SPI Device 10-Byte Header for Block 1 L1 Memory Block 1 Block 1 10-Byte Header for Block 2 Block 3 Block 2 ..App. Code/ 10-Byte Header for Block 3 Data Block 3 ..

  • Page 49: Adsp-Bf531/Bf532/Bf533 Processor Boot Streams

    Blackfin Processor Loader/Splitter ADSP-BF531/BF532/BF533 Processor Boot Streams The following sections describe the boot stream, header, and flag frame- work for ADSP-BF531, ADSP-BF532, and ADSP-BF533 processors. • “Blocks and Block Headers” on page 2-19 • “Flags of Block Header” on page 2-20 •...

  • Page 50: Flags Of Block Header

    Blackfin Processor Booting B lo c k H e a de r fo r D X E 1 C ou n t 1 0 -B y te H ea d e r DXE1 Byte Count 4 -B y te A d dr es s Header for Block 1 4 -B y te C ou n t Block 1...

  • Page 51: Initialization Blocks

    Blackfin Processor Loader/Splitter Table 2-4. Flag Structure Bit Field Description Zero-Fill Block Indicates that the block is a buffer filled with zeros. Zero Block is not included within loader file. When the loader parses through the . file and encounters a large buffer with zeros, it creates a zero-fill block to reduce .
  • Page 52 Blackfin Processor Booting ADSP-BF531/BF532/BF533 Processor PROM/Flash or SPI Device Header for Init Block L1 Memory Init Block Init Block 1eader for L1 Block L1 Block App. Code/ Header for SDRAM Block Data SDRAM Block ..10-Byte Header for Block n Block n 0xEF00 0000 On-Chip...
  • Page 53 Blackfin Processor Loader/Splitter Listing 2-1. Initialization Block Code Example This file contains 3 sections: */ 1) A Pre-Init Section–this section saves off all the DSP registers onto the stack. 2) An Init Code Section–this section is the initialization code which can be modified by the customer As an example, an SDRAM initialization code is supplied.
  • Page 54 Blackfin Processor Booting P0.H = (EBIU_SDRRC >> 16) & 0xFFFF; R0 = 0x074A(Z); W[P0] = R0; SSYNC; P0.L = EBIU_SDBCTL & 0xFFFF; /* SDRAM Memory Bank Control Register */ P0.H = (EBIU_SDBCTL >> 16) & 0xFFFF; R0 = 0x0001(Z); W[P0] = R0; SSYNC;...

  • Page 55: Adsp-Bf531/Bf532/Bf533 Processor Memory Ranges

    Blackfin Processor Loader/Splitter ADSP-BF531/BF532/BF533 Processor Memory Ranges The on-chip boot ROM on ADSP-BF531, ADSP-BF532, and ADSP-BF533 Blackfin processors allows booting to the following memory ranges. • L1 memory • ADSP-BF531 processor Data Bank A SRAM ( – " 0xFF80 4000 0xFF80 7FFF Instruction SRAM ( –...

  • Page 56: Adsp-Bf531/Bf532/Bf533 Processor Spl Memory Boot Sequence

    Blackfin Processor Booting ADSP-BF531/BF532/BF533 Processor SPl Memory Boot Se- quence The ADSP-BF531/BF532/BF533 processors support booting from 8-, 16-, or 24-bit addressable SPI memories ( BMODE = 11 To determine the memory type connected to the processor (8-, 16-, or 24-bit), the processor sends signals to the SPI memory until it responds back.
  • Page 57 ”, which, based on a Baud Rate 133 MHz system clock, results in a 133 MHz/(2*133) = 500 kHz baud rate. Analog Devices recommends the following SPI memory devices. • 8-bit addressable SPI memory: 25LC040 from Microchip http://www.microchip.com/download/lit/pline/mem- ory/spi/21204c.pdf • 16-bit addressable SPI memory: 25CL640 from Microchip http://www.microchip.com/download/lit/pline/mem-...

  • Page 58: Adsp-Bf561 Processor Booting

    Blackfin Processor Booting ADSP-BF561 Processor Booting The booting sequence for the ADSP-BF561 dual-core processor is similar to the ADSP-BF531/BF532/BF533 processor booting sequence (described on page 2-16). Differences occur because the ADSP-BF561 processor has two cores: core A and core B. After reset, core B remains idle, but core A executes the on-chip boot ROM located at address 0xEF00 0000 Please refer to Chapter 3 of the ADSP-BF561 Hardware Reference...

  • Page 59: Adsp-Bf561 Processor Boot Streams

    Blackfin Processor Loader/Splitter ISR. The boot ROM then checks to see if it has been invoked by a soft- ware reset by examining bit 4 of the System Reset Configuration Register SYSCR If bit 4 is not set, the boot ROM presumes that a hard reset has occurred and performs the full boot sequence.
  • Page 60 Blackfin Processor Booting Unlike the ADSP-BF531/BF532/BF533 processor, the ADSP-BF561 boot stream begins with a 4-byte global header, which contains informa- tion about the external memory device. The global header also contains a signature in the upper 4 bits that prevents the boot ROM from trying to read a boot stream from a blank device.
  • Page 61 Blackfin Processor Loader/Splitter For the count block, the address field is irrelevant since the block is .DXE not going to be copied to memory. The “ignore bit” is set in the flag word of this header, so the boot loader does not try to load the count but .DXE skips the count.
  • Page 62 Blackfin Processor Booting Table 2-7. ADSP-BF561 Processor Boot Stream Structure (Cont’d) Bit Field Description of the first 1st byte count 120–127 8–15 .DXE of the first 1st byte count 128–135 16–23 .DXE of the first 1st byte count 136–143 24–31 .DXE LSB of the address field of the 1st data block in 1st 144–151...
  • Page 63 Blackfin Processor Loader/Splitter Table 2-7. ADSP-BF561 Processor Boot Stream Structure (Cont’d) Bit Field Description of the byte count field of the nth block of 1st … 8–15 .DXE of the byte count field of the nth block of 1st … 16–23 .DXE MSB of the byte count field of the nth block of 1st...

  • Page 64: Adsp-Bf561 Processor Memory Ranges

    Blackfin Processor Booting ADSP-BF561 Processor Memory Ranges The on-chip boot ROM of the ADSP-BF561 processor can load a full application to the various memories of both cores. Booting is allowed to the following memory ranges. The boot ROM clears these memory ranges before booting in a new application.

  • Page 65: Adsp-Bf561 Processor Initialization Blocks

    Blackfin Processor Loader/Splitter The boot ROM does not support booting to core A scratch mem- ory ( – ) and to core B scratch memory 0xFFB0 0000 0xFFB0 0FFF – ). Data that needs to be initialized prior 0xFF70 0000 0xFF70 0FFF to runtime should not be placed in scratch memory.

  • Page 66: Adsp-Bf561 Multiple .Dxe Booting

    Blackfin Processor Booting ADSP-BF561 Multiple .DXE Booting A typical dual-core application is separated into two executable files; one for each core. The default linker description files (LDFs) for the ADSP-BF561 processor creates two separate executable files ( p0.dxe ) and some shared memory files ( ).

  • Page 67: Adsp-Bf531/Bf532/Bf533 And Adsp-Bf561 Multiple .Dxe Booting

    Blackfin Processor Loader/Splitter ADSP-BF531/BF532/BF533 and ADSP-BF561 Multiple .DXE Booting This section describes how to boot more than one file into a .DXE ADSP-BF531/BF532/BF533 and ADSP-BF561 processor. The informa- tion presented in this section applies to all of the named processors. For additional information on the ADSP-BF561 processor, refer to “ADSP-BF561 Multiple .DXE Booting”...
  • Page 68 Blackfin Processor Booting 10-Byte Header for Count 10-Byte H eader for Block 1 4-Byte Count for 1st DXE Block 1 10-Byte H eader for Block 2 1st DXE Application Block 2 10-Byte H eader for Block 3 10-Byte Header for Count Block 3 ......
  • Page 69 Blackfin Processor Loader/Splitter Listing 2-2. Initialization Block Code Example for Multiple .DXE Boot #include <defBF532.h> .SECTION program; /*******Pre-Init Section***************************************/ [--SP] = ASTAT; [--SP] = RETS; [--SP] = (r7:0); [--SP] = (p5:0); [--SP] = I0;[--SP] = I1;[--SP] = I2;[--SP] = I3; [--SP] = B0;[--SP] = B1;[--SP] = B2;[--SP] = B3;...

  • Page 70: Blackfin Processor Loader Guide

    Blackfin Processor Loader Guide Blackfin Processor Loader Guide Loader operations depend on the loader options, which control how the loader processes executable files, letting you select features such as boot mode, boot kernel, and output file format. These options are specified on the loader’s command line or via the Load page of the Project Options dialog box in the VisualDSP++ environment.

  • Page 71: File Searches

    Blackfin Processor Loader/Splitter where: • —Name of the executable file ( ) to be processed sourcefile .DXE into a single boot-loadable or non-bootable file. An input file name can include the drive and directory. For multiprocessor or multiin- put systems, specify multiple input s.

  • Page 72: Command-Line Switches

    Blackfin Processor Loader Guide Table 2-8. File Extensions Extension File Description Loader input files, boot-kernel files, and initialization files. .DXE Loader output file. .LDR Loader output files containing kernel code only when two output files are selected. .KNL Command-Line Switches A summary of the loader command-line switches appear in Table 2-9.
  • Page 73 Blackfin Processor Loader/Splitter Table 2-9. Blackfin Loader Command-Line Switches (Cont’d) Switch Description Invokes the command-line help, outputs a list of command-line switches to standard output, and exits. By default, the switch alone provides help for the loader driver. To obtain a help screen for your -help target Blackfin processor, add the switch to the command...
  • Page 74 Blackfin Processor Loader Guide Table 2-9. Blackfin Loader Command-Line Switches (Cont’d) Switch Description Specifies a hex PROM/Flash output start address for kernel code. A -kp # valid value is between [ ]. The specified value will 0xFFFFFFFF not be used if no kernel or/and initialization code is included in the loader file.
  • Page 75 Blackfin Processor Loader/Splitter Table 2-9. Blackfin Loader Command-Line Switches (Cont’d) Switch Description Specifies the make dependencies target output filename. -Mt filename option is for use with either the or - option. If not present, the default is the name of the input file with the . extension.
  • Page 76 Blackfin Processor Loader Guide Table 2-9. Blackfin Loader Command-Line Switches (Cont’d) Switch Description Displays a message returned from the encryption function. -ShowEncryptionMessage Provides a silicon revision of the specified processor. -si-revision version parameter represents a silicon revision of the processor version specified by the switch.

  • Page 77: Using Base Loader

    Blackfin Processor Loader/Splitter Using Base Loader The Load page of the Project Options dialog consists of multiple panes and is the same and for all Blackfin processors. When you open the Load page, the default loader settings (Loader options) for the selected proces- sor are already set.
  • Page 78 Blackfin Processor Loader Guide Using the page controls, you can select or modify the loader settings. Table 2-10 describes each loader control and corresponding setting. When you are satisfied with default settings, click OK to complete the loader setup. Table 2-10. Base Loader Page Settings Setting Description Category...

  • Page 79: Using Second-Stage Loader

    Blackfin Processor Loader/Splitter Table 2-10. Base Loader Page Settings (Cont’d) Setting Description Baud rate Specifies a baud rate for SPI booting ( kHz, MHz, and MHz). The selection is active for ADSP-BF535 processors. For ADSP-BF531, ADSP-BF532, and ADSP-BF533 processors, the field is grayed out. Initialization Directs the loader to include the initialization file (Init code).
  • Page 80 Blackfin Processor Loader Guide -kp # -kwidth -l filename Figure 2-15. ADSP-BF53x Processors: Boot Kernel Pane 3. Select Use boot kernel. By default, this option is selected for ADSP-BF535 and grayed out for ADSP-BF531/BF532/BF533 and ADSP-BF561 processors. 4. If you want to produce two output files (boot kernel file and appli- cation code file), select the Output kernel in separate file check box.

  • Page 81: Using Rom Splitter

    Blackfin Processor Loader/Splitter 5. Enter the Kernel file ( ). You must either use the default kernel .DXE (in case of a ADSP-BF535 processor) or enter a kernel filename if Use boot kernel in step 3 is selected. The following second-stage loaders are currently available for the ADSP-BF535 processor.
  • Page 82 Blackfin Processor Loader Guide splitter utility is controlled by the LDF’s command. Segments TYPE() declared with are consumed by the loader utility, and segments TYPE(RAM) declared by are consumed by the splitter. TYPE(ROM) Figure 2-16 shows an example ROM splitter options pane of the Load page.

  • Page 83: No-Boot Mode

    Blackfin Processor Loader/Splitter becomes . The valid numbers are integers 0x2000 0000 0x0000 0000 through but, based on your specific input file, the value can be within a subset of [ No-boot Mode The hardware settings of for ADSP-BF535 processors or BMODE = 000 for ADSP-BF531, ADSP-BF532, and ADSP-BF533 proces- BMODE = 00...
  • Page 84 Blackfin Processor Loader Guide Listing 2-4. ROM Segment Definitions (LDF File) PROCESSOR p0 OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) SECTIONS program_rom INPUT_SECTION_ALIGN(4) INPUT_SECTIONS( $OBJECTS(rom_code) ) } >MEM_PROGRAM_ROM data_rom INPUT_SECTION_ALIGN(4) INPUT_SECTIONS($OBJECTS(rom_data) ) } >MEM_DATA_ROM data_sram INPUT_SECTION_ALIGN(4) INPUT_SECTIONS($OBJECTS(ram_data) ) } >MEM_DATA_RAM With the LDF file modified this way, the source files can now take advan- tage of the newly introduced sections, as in Listing 2-5.
  • Page 85 Blackfin Processor Loader/Splitter /* . . . */ .SECTION rom_data; .VAR myconst x = 0xdeadbeef; /* . . . */ .SECTION ram_data; .VAR myvar y; /* note that y cannot be initialized automatically */ VisualDSP++ Loader Manual 2-55 for 16-Bit Processors...
  • Page 86 Blackfin Processor Loader Guide 2-56 VisualDSP++ Loader Manual for 16-Bit Processors...

  • Page 87: Adsp-219X Dsp Loader/Splitter

    3 ADSP-219X DSP LOADER/SPLITTER This chapter explains how the loader/splitter program ( ) is elfloader.exe used to convert executable files (. ) into boot-loadable, no-bootable, or combined output files for ADSP-219x DSPs. “ADSP-219x loader/splitter” refers to the loader/splitter program designed for ADSP-2191, ADSP-2195, ADSP-2196, ADSP-21990, ADSP-21991, and ADSP-21992 DSPs.

  • Page 88: Adsp-219X Dsp Booting

    ADSP-219x DSP Booting ADSP-219x DSP Booting The ADSP-219x loader/splitter creates a boot stream, non-boot stream, or combinational output. The program accepts one executable file ( ) as .DXE input and generates one file (. ) as output. Upon powerup, a ADSP-219x DSP can be booted from the EPROM, UART, SPI, or Host port.

  • Page 89: Adsp-219X Dsp Boot Modes

    ADSP-219x DSP Loader/Splitter ADSP-219x DSP Boot Modes At powerup, after the reset, the processor transitions into a boot mode sequence configured by the pins. The pins are dedicated BMODE2–0 BMODE mode-control pins; the pin states are captured and placed in the Reset Configuration register as , and (see...

  • Page 90: Adsp-219X Dsp Boot Kernel

    ADSP-219x DSP Booting ADSP-219x DSP Boot Kernel A loader boot kernel refers to the resident program stored in a 24-bit-wide, 1K portion of ROM space responsible for booting the DSP. The starting address of the boot ROM is , the first 0xFF 0000 0xFF 03FF location of page 256, in 1-wait-stated memory.

  • Page 91: Block Headers

    ADSP-219x DSP Loader/Splitter This first header is followed by the regular boot stream, that is, a series of headers and data blocks. Most headers are followed by corresponding blocks of data, but some headers indicate regions of memory that need to be “zero-filled”...

  • Page 92: Data Blocks

    ADSP-219x DSP Booting controlled by the mode pins. The width information configures the EMI interface and remains valid during the entire boot process. If you want to boot off-chip memories, be aware that the width of the memory you want to boot must be identical to the width of the interface from which you are booting.

  • Page 93: Adsp-219X Dsp Multiple .Dxe Support

    ADSP-219x DSP Loader/Splitter ADSP-219x DSP Multiple .DXE Support VisualDSP++ 3.5 introduces support for multiple booting in Parallel .DXE EPROM booting mode. Boot streams of multiple projects or applications can be stored in a single EPROM. The on-chip boot kernel always boots in application number 0.
  • Page 94 ADSP-219x DSP Booting If more than one file is listed at the command line without .DXE switch, the loader utility appends the boot stream of the second .DXE immediately to the one of the first and so on. Executable files inherit .DXE boot stream settings from previous one if not explicitly set by a grouping.
  • Page 95 ADSP-219x DSP Loader/Splitter Output file ( ) for the current and following s (see “-o filename” on .LDR .DXE page 3-22). Opmode for the current and following . s (see “-opmode #” on page 3-22). -opmode The Intel hex offset for the current loader file (see “-p address”...

  • Page 96: Host Booting

    ADSP-219x DSP Booting elfloader -proc ADSP-2191 -b PROM -width 16 app1.dxe app2.dxe -pdAddrNext 0x20000 elfloader -proc ADSP-2191 -b PROM -width 8 -o flash.ldr -pd 0x20000 -p 0x20000 app3.dxe -pd 0x30000 app4.dxe In cases where the values are expected to be the same, you may specify -pEqualPD elfloader -proc ADSP-2191 -b PROM -width 16 app1.dxe...

  • Page 97: Uart Booting

    ADSP-219x DSP Loader/Splitter It is recommended that the host parses the boot stream and downloads segment by segment. The may store the boot stream as an elfloader.exe Intel hex-32 file typically required by embedded host devices. PC-based hosts may favor the ASCII format, which stores one byte or one 16-bit word per line.

  • Page 98: Serial Eprom Booting

    ADSP-219x DSP Booting Serial EPROM Booting The SPI0 port is used when booting from an SPI-compatible EPROM. The SPI port selects a single serial EPROM device using the pin as a chip select, submits a read command and address , and begins to 0x00 clock consecutive data into memory (internal memory or external mem- ory) at a...
  • Page 99 ADSP-219x DSP Loader/Splitter signal ( ). Splitter capabilities of the ADSP-219x loader utility support /MS0 the generation of the required EPROM image files. Refer to the loader’s switch (see on page 3-23) for more information. -romsplitter Non-bootable memory segments are declared by the command TYPE(ROM) in the Linker Description File (...
  • Page 100 ADSP-219x DSP Booting The data segment is defined by the command, seg_ext_data TYPE(DM) which sets the logical width to 16 bits. Since the command also WIDTH(16) sets the physical width to 16 bit, no data packing and no address multiply is required.
  • Page 101 ADSP-219x DSP Loader/Splitter Table 3-3. EPROM Image—Two Segments Only Address range Purpose seg_ext_data 0x000000 - 0x00FFFF 0x010000 - 0x01FFFF seg_ext_code Typically, the loader utility generates an Intel hex-32 file, which is read- able by most EPROMs. If the image must be post-processed, the loader may also generate ASCII files.

  • Page 102: Enriching Boot Eproms With No-Boot Data

    ADSP-219x DSP Booting 789ABC DEF012 345678 9ABCDE F01234 56789A BCDEF0 // 8th (last) data word optional, // controlled by the -checksum switch Enriching Boot EPROMs with No-boot Data The loader’s splitter functionality (refer to “No-booting” on page 3-12) enables powerful memory utilization in combination with the parallel EPROM boot mode.
  • Page 103 ADSP-219x DSP Loader/Splitter Table 3-4. EPROM Image With No-boot Data Address range Purpose Boot stream 0x000000–0x009FFF (External read-only data) seg_ext_data 0x00A000–0x00AFFF (External program) 0x00B000–0x00FFFF seg_ext_code divided by 2 to obtain the corresponding logical address. The first alias window of that can accessed properly is range seg_ext_data 0x02 A000 ;...
  • Page 104 ADSP-219x DSP Booting switch (see on page 3-22). Then all EPROM addresses are -maskaddr 16 ANDed by , and the resulting EPROM image fits into a 64-Kbyte 0xFFFF EPROM. The EPROM boot process assumes the boot device is connected to the DSP’s strobe.

  • Page 105: Adsp-219X Dsp Loader Guide

    When using the loader within VisualDSP++, settings on the Load page of the Project Options dialog box correspond to the loader’s command-line switches. For more information, see the VisualDSP++ 3.5 User’s Guide for 16-Bit Processors or online Help. ADSP-219x Loader Command-Line Reference Use the following syntax for the loader’s command line.

  • Page 106: File Searches

    ADSP-219x DSP Loader Guide Example: elfloader p0.dxe -proc ADSP-2191 In the above example, the loader runs with: • —the name of the executable file to be processed into a p0.dxe boot-loadable file. The output file’s name is because a name p0.ldr is not specified.

  • Page 107: Loader Switches

    ADSP-219x DSP Loader/Splitter Loader Switches A description of each loader command-line switch appears in Table 3-6. Table 3-6. Loader Command-Line Switches Switch Description Specifies an executable file to be processed into a single-processor load- filename able file. For multiprocessor system, use the switch.
  • Page 108 ADSP-219x DSP Loader Guide Table 3-6. Loader Command-Line Switches (Cont’d) Switch Description Writes make dependencies to the named specified. -Mo filename option is for use with either the or - option. If is not present, the default is display. <stdout> Specifies the make dependencies target name.
  • Page 109 ADSP-219x DSP Loader/Splitter Table 3-6. Loader Command-Line Switches (Cont’d) Switch Description Appends another application program ( ) at the specified address. address .DXE You can specify options applicable to the boot-stream general header inputfile between . If no ] is specified, address inputfile address...
  • Page 110 ADSP-219x DSP Loader Guide Table 3-6. Loader Command-Line Switches (Cont’d) Switch Description Determines the number of wait states for external accesses. Valid inputs -waits # (inclusive). Default is Note: For EPROM and Host boot modes only. Specifies the bus width (in bits) for EPROM/Flash or Host booting. -width # Valid numbers are (default) and...

  • Page 111: Adsp-2192-12 Dsp Loader

    4 ADSP-2192-12 DSP LOADER This chapter explains how the loader program ( ) is used to elfloader.exe convert executable files ( ) into boot-loadable files ( ) for .DXE ADSP-2192-12 DSPs. You cannot produce a non-bootable PROM image file (that is, splitting is not supported) for an ADSP-2192-12 DSP.

  • Page 112: Adsp-2192 Dsp Booting

    ADSP-2192 DSP Booting ADSP-2192 DSP Booting An ADSP-2192-12 DSP can be boot-loaded through its PCI or USB interface. For PCI loading, the loadable executable ( ) must reside in .EXE the PC host’s memory space before it is loaded into the DSP. The ADSP-2192-12 loader repackages files and associated .DXE...
  • Page 113 ADSP-2192-12 DSP Loader Upon recovering from , the ADSP-2192 DSP jumps to the first RESET location of the boot ROM at address , which is the start of the 0x14000 boot kernel. The first task performed by the kernel is to determine the type of and the source of booting (PCI or USB).

  • Page 114: Adsp-2192 Dsp Rtbl

    ADSP-2192 DSP Booting Once the bus configurations have been determined (assuming that a serial EEPROM exists), the boot kernel calls a function to commence reading data from the serial EEPROM. Data format of serial EEPROM boot stream is described in the “ADSP-2192 DSP RTBL”...

  • Page 115: Building .Dxe Files

    ADSP-2192-12 DSP Loader .SM File 1.DXE 2.DXE .OVL File Loader: The loader consumes the linker’s output files (.DXE) to produce a RTBL: C-language source file (.H) The run-time boot loader compiles that contains data .H File .C Files the.H file and any other source files structures representing the (typically, C/C++) using host deve- executable.

  • Page 116: Creating A .Exe File

    .DXE .OVL For more information about the VisualDSP++ IDDE, see the VisualDSP++ 3.5 User’s Guide for 16-bit Processors or online Help. If a DSP executable file changes, rerun the loader. The rerun creates a new file from the , and input files.

  • Page 117: Reference Rtbl

    ADSP-2192-12 DSP Loader To create an file from VisualDSP++ .EXE 1. From the Load page of the Project Options dialog box, specify the input ( ) files under Core 0 and Core 1. .DXE 2. From the Post Build page, configure one or more command lines to execute the RTBL.

  • Page 118: Adsp-2192 Dsp Rbtl And Overlays

    ADSP-2192 DSP Booting The EZ-KIT Lite evaluation system driver can be reused for targets other than Analog Devices EZ-KIT Lite evaluation systems, but this simple driver may be inadequate for anything other than prototyping. Further- more, the EZ-KIT Lite driver can be reused only on so-called “plug-and-play”...

  • Page 119: Using Overlay Symbols

    ADSP-2192-12 DSP Loader Using Overlay Symbols The loader utility, when running, searches for the OvlPciAdrTbl symbols. If the loader cannot resolve the two symbols, it sets OvlMgrTbl both values to zero. You must declare one or both symbols in the assembly source file to make the run-time loader handle the overlay properly.

  • Page 120: Adsp-2192 Dsp Loader Guide

    When using the loader from within VisualDSP++, settings on the Load page of the Project Options dialog box correspond to the loader’s com- mand-line switches. For more information, see the VisualDSP++ 3.5 User’s Guide for 16-bit Processors or online Help.

  • Page 121: Two-Processor Command Line

    ADSP-2192-12 DSP Loader • —Optional name of the loader’s output, a C-lan- -o outputfile guage header file ( • —The mandatory switch directs the loader to -proc ADSP-2192 produce an output file for the ADSP-2192 processor. • —One or more optional switches to pass to the loader. -switch…...

  • Page 122: File Searches

    ADSP-2192 DSP Loader Guide Example elfloader -proc ADSP-2192 -core0 p0.dxe -core1 p1.dxe This command line runs the loader utility with: • —Directs the loader to produce an output file for -proc ADSP-2192 the ADSP-2192-12 processor. • —Identifies the input file ( ) to be processed -core0 p0.dxe p0.dxe...

  • Page 123: File Extensions

    ADSP-2192-12 DSP Loader File Extensions Table 4-3 lists and describes file types input and output by the loader. Table 4-3. ADSP-2192 DSP Loader File Extensions File Extension Description Executable files. .DXE Overlay memory files. The loader recognizes overlay memory files but does not .OVL expect these files on the command line.
  • Page 124 ADSP-2192 DSP Loader Guide Table 4-4. ADSP-2192 DSP Loader Command-Line Switches (Cont’d) Switch Description Writes make dependencies to the named file. -Mo filename option is for use with either the or - option. If not present, the default is a display.

  • Page 125: Adsp-218X Dsp Loader/Splitter

    .LDR .BNL .BNM ). The preparation of a non-bootable image is also called splitting (or .BNU PROM splitting). In most cases, developers working with ADSP-218x DSPs use the loader instead of the splitter. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 126: Boot Modes

    A fully debugged program can be automatically downloaded to the proces- sor after power-up or after a software reset. The way the loader creates a boot-loadable file depends upon how your program is booted into the DSP (booting mode). VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 127 24-bit PROM mem- ory. The splitter capabilities of the generate a proper PROM hex elfspl21 file. This option is not often used. You must run from a elfspl21.exe command line. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 128: Determining Boot Modes

    No automatic boot operations occur. Program execu- tion starts at external memory location 0. The chip is configured in Full Memory Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 129 Table 5-3 lists DSPs that support Mode D operation ( pin). Mode D Table 5-3. ADSP-218x DSPs Supporting Mode D Operation ADSP-2184N ADSP-2185M ADSP-2185N ADSP-2186M ADSP-2186M ADSP-2187L ADSP-2187N ADSP-2188M ADSP-2188N ADSP-2189M ADSP-2189N VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 130: Eprom Booting (Bdma)

    /* BDMA IRQ 0x0008: 3C008C 000000 */ imask = 0x0008; /* 0x000A: 3C0083 */ idle; /* 0x000B: 028000 */ jump 0x0020; nop; nop; nop; /* 0x000C: 18020F 000000 */ nop; nop; nop; nop; /* 0x0010: 000000 000000 */ VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 131: Adsp-218X Bdma Loader Command-Line Reference

    The default file extension is . BNM. ADSP-218x BDMA Loader Command-Line Reference This section details the ADSP-218x BDMA loader’s command-line interface. The syntax for the loader’s command line is: elfspl21 sourcefile [outputfile] -218{x|1} [-switch …] VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 132 —the name of the executable file to process into a p0.dxe boot-loadable file. • —the name of the loader output file. output.bnm • —the target processor, one of the ADSP-2184 through -218x ADSP-2189 DSPs. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 133: File Searches

    .DXE file. .BNM Loader output file for EPROMs. .BNM Loader output file for IDMA. .IDM Loader Switches Table 5-5 lists and describes the loader switches used in BDMA mode. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 134 0x4000 -bdma loader and page loaders for the specified file. This way, two or .DXE more applications can be stored in the same EPROM and may replace the default application at runtime. 5-10 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 135: Host Booting (Idma)

    ADSP-2189 DSPs only). Afterwards, the host writes 16- or 24-bit words to the IDMA port. The DSP auto-increments its address counter. Figure 5-1 on page 5-12 illustrates the algorithm the host processor must compute to boot the DSP successfully. VisualDSP++ 3.5 Loader Manual 5-11 for 16-Bit Processors...
  • Page 136 It is up to the user to post-process this file in a customized .IDM way. Due to hardware restrictions, IDMA booting of off-chip memories is not possible. Refer to the description of IDMA capabilities in the ADSP-218x DSP Hardware Reference. 5-12 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 137: Adsp-218X Idma Loader Command-Line Reference

    Preparing a non-bootable PROM image is called splitting. In most cases, developers working with ADSP-218x DSPs use the loader instead of the splitter. For ADSP-218x DSPs, splitter and loader features are handled by VisualDSP++ 3.5 Loader Manual 5-13 for 16-Bit Processors...
  • Page 138 ADSP-218x DSP Loader Guide . The splitter must be invoked by a completely different elfspl21.exe set of command-line switches. Refer to the following “ADSP-218x DSP Splitter Guide” for more information. 5-14 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 139: Adsp-218X Dsp Splitter Guide

    1 and 2), the generated code must target ROM. Define the appropriate ROM segments in the file. .LDF Splitter options control how the splitter processes executable files, letting you select features such as memory type and file format. VisualDSP++ 3.5 Loader Manual 5-15 for 16-Bit Processors...

  • Page 140: Adsp-218X Splitter Command-Line Reference

    The following two command lines run the splitter twice, first producing PROM files for program memory and then producing PROM files for data memory. elfspl21 my_proj.dxe pm_stuff -pm elfspl21 my_proj.dxe dm_stuff -dm 5-16 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 141 When you provide an input or output file name as a command-line parameter, use the guidelines stated on page 1-9. Splitter File Extensions Table 5-7 lists and describes file types input and output by the splitter. VisualDSP++ 3.5 Loader Manual 5-17 for 16-Bit Processors...
  • Page 142 —contains the middle bytes .BNM —contains the lowest bytes. .BNL Includes RAM and ROM in PROM. -readall Extracts both RAM and ROM segments from the input file. By default, only ROM segments are extracted. 5-18 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...
  • Page 143 Switch Description Produces Motorola S1 output format Produces a byte-stacked format file for 8-bit memory: yields Motorola S1 output format -us2 yields Motorola S2 output format -us2 yields Intel hex output format. VisualDSP++ 3.5 Loader Manual 5-19 for 16-Bit Processors...
  • Page 144 ADSP-218x DSP Splitter Guide 5-20 VisualDSP++ 3.5 Loader Manual for 16-Bit Processors...

  • Page 145: File Formats

    A FILE FORMATS VisualDSP++ development tools support many file formats, in some cases several for each development tool. This appendix describes file formats that are prepared as inputs and produced as outputs. The appendix describes three types of files: • “Source Files”...

  • Page 146: Source Files

    The C/C++ compiler, run-time library, as well as a definition of ADI extensions to ANSI C are detailed in your target processor’s VisualDSP++ 3.5 C/C++ Compiler and Library Manual. With and without built-in function support; a minimal differentiator. There are others.

  • Page 147: Assembly Source Files

    Preprocessor commands control macro processing and conditional assem- bly or compilation. For information on the assembler and preprocessor, see the VisualDSP++ 3.5 Assembler and Preprocessor Manual. Assembly Initialization Data Files Assembly initialization data files ( ) are text files that contain fixed- or .DAT...

  • Page 148: Header Files

    Linker Description Files are ASCII text files that contain commands .LDF for the linker in the linker’s scripting language. For information on this scripting language, see the VisualDSP++ 3.5 Linker and Utilities Manual for 16-Bit Processors. VisualDSP++ Loader Manual for 16-Bit Processors...

  • Page 149: Linker Command-Line Files

    ) are ASCII text files that contain .TXT command-line input for the linker. For more information on the linker command line, see the VisualDSP++ 3.5 Linker and Utilities Manual for 16-Bit Processors. Build Files Build files are produced by the VisualDSP++ development tools while building a project.

  • Page 150: Build Files

    Build Files Library Files Library files ( ), the archiver’s output, are binary, executable and link- .DLB able files (ELF). Library files (called archive files in previous software releases) contain one or more object files (archive elements). The linker searches through library files for library members used by the code.

  • Page 151: Memory Map Files

    File Formats Memory Map Files The linker can output memory map files ( ), which are ASCII text files .MAP that contain memory and symbol information for your executable file(s). The map contains a summary of memory defined with com- MEMORY{} mands in the file, and provides a list of the absolute addresses of all...
  • Page 152 Build Files Table A-2. Extended Linear Address Record Example Field Purpose Example record :020000040000FA Start character Byte count (always 02) Address (always 0000) 0000 Record type Offset address 0000 Checksum Table A-3. Data Record Example Field Purpose Example record :0402100000FE03F0F9 Start character Byte count of this record Address...

  • Page 153: Splitter Output Files In Ascii Format

    File Formats Table A-4. End-of-File Record Example (Cont’d) Field Purpose Record type Checksum Splitter Output Files in ASCII Format When the loader is invoked as a splitter, its output can be an ASCII-for- mat file with the extension. ASCII-format files are text .LDR representations of ROM memory images that can be post-processed by users.

  • Page 154: Format References

    Format References In the following example (Table A-5), a SPORT register is set for 20-bit words and the data file contains hexadecimal numbers. The simulator con- verts the hex numbers to binary and then fills/truncates to match the SPORT word size. The is filled and is truncated.
  • Page 155 INDEX Symbols .TXT ASCII text files .ALIGN directive 2-14 .ASM assembly files Numerics .BNL splitter output files 5-1, 5-18 16-bit addressable SPI memory 2-27 .BNM loader output files 5-7, -2184|5|6|8|9 loader switch 5-10, 5-13 .BNM splitter output files 5-1, 5-18 -218x|1 loader switch 5-10, 5-13 .BNU loader output files...
  • Page 156 INDEX -offsetaddr # 5-11 loader 4-2, -offsetpage # 5-11 ADSP-2192-12 loader switches -s (S2 format) 5-10 -f format 4-13 -uload file 5-11 4-13 ADSP-218x loader/splitter 4-13 ADSP-218x processors -Mo filename 4-14 loader -Mt filename 4-14 ADSP-218x splitter 5-15 -o filename 4-14 command-line switches 5-18...
  • Page 157 INDEX -proc processor 3-23 memory bank 0 2-53 -readall 3-23 -romsplitter 3-23 -split # 3-23 -b (boot mode) loader switch 2-42, 3-21 -verbose 3-23 baud rate 2-49 -waits # 3-24 -baudrate loader switch 2-42 -width # 3-24 BDMA ADSP-219x loader/splitter interface 5-3, ADSP-BF531/BF532/BF533 transfers...
  • Page 158 INDEX -Mo filename 2-44 flags 2-13 -Mt filename 2-45 headers 2-13, 2-18, 2-30, 2-35, -no2kernel 2-45 structure 2-19 -o filename 2-45 -blocksize # loader switch 3-21 -o2 (two output files) 2-45 BMODE pin settings -p # 2-45 ADSP-2181 DSPs -proc processor 2-45 ADSP-2183 DSPs -romsplitter...
  • Page 159 INDEX boot ROM 1-7, 2-3, 2-6, 2-18, 2-29, serial EPROM 3-12 2-36 UART part 3-11 boot sequences 1-4, via UART on ADSP-219x 3-11 ADSP-BF531/32/33 processors 2-16 without boot kernel 2-45 ADSP-BF535 processors boot-loadable files 1-4, boot streams 2-35 bootstraps 2-45, 5-4, ADSP-219x build ADSP-219x DSPs...
  • Page 160 INDEX core EMICTL register 3-24 A ranges 2-34 emulator B ranges 2-34 -enc dll_filename loader switch 2-42 count EPROM blocks 2-30 output 2-8, 2-42 headers 2-35, 2-37 with no-boot data 3-16 creating run-time boot loader excluding ADSP-218x loader 5-10 Executable and Linkable Format (ELF) executable files 1-4, data External Bus Interface Unit (EBIU)
  • Page 161 INDEX .LDR (ASCII-format) .LDR (hex format) headers 2-37 build block headers 2-13 C/C++ -help loader switch 2-43, 3-21, 4-13, data files 5-10 debugger hex-format files executable .LDR format references A-10 -HoldTime # loader switch 2-43 formats host booting input ADSP-218x DSPs 5-5, 5-11 library host booting mode, overview...
  • Page 162 INDEX build options for ADSP-218x processors -k (kernel width) loader switch 2-44 hex-format files -kb (boot mode) loader switch 2-43 settings selection 3-21, 4-13, -kenc dll_filename loader switch 2-42 -loader loader switch 5-10 kernel file option 2-49 kernels see also boot kernel -kf (kernel format) loader switch 2-43 -M loader switch 2-44, 3-21,...
  • Page 163 INDEX ADSP-BF535 processors -pEqualPd loader switch 3-22 Blackfin processors 2-53 -pEqualZero loader switch 3-22 overview pm memory 5-7, 5-11 selecting 2-48, 2-53 -pm splitter switch 5-18 -NoDxeAddrHdr loader switch 3-22 PMOVLAY memory page 5-15 -noloader loader switch 5-10 power-ups non-bootable files 1-4, 2-45, preloader 5-10 preloaders, ADSP-218x DSPs...
  • Page 164 INDEX file formats A-10 silicon revision setting 2-46, 4-14 reset 2-2, 2-3, 2-16, 5-2, 5-6, 5-11 simulating booting process ADSP-2192 DSPs simulator 1-2, RESET interrupt 2-17, 2-28 -si-revision loader switch 4-14 -si-revision loader switch 2-46 images 5-15 slave processors 1-4, 5-11 memory 5-18...
  • Page 165 INDEX see boot streams VisualDSP++ supervisor mode 2-28 Load page 5-2, SYSCR register 2-5, 2-29 Load page, Boot kernel options 2-49 ADSP-BF531/32/33 processors 2-17 Load page, ROM splitter options 2-52 ADSP-BF535 processors 2-2, wait states 2-46, 2-48, -uload file loader switch 5-11 -waits loader switch 2-46, 3-24...
  • Page 166 INDEX I-12 VisualDSP++ Loader Manual for 16-Bit Processors...

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