Analog Devices VisualDSP++ 3.5 Manual page 50

Link Target Description
The device has two ports to the L2 memory: one dedicated to core
requests, and the other dedicated to system DMA and PCI requests. The
processor units can process 8-, 16-, 32-, or 40-bit data, depending on the
type of function being performed.
Memory ranges are listed in
are reserved.
Table 2-1. ADSP-BF535 Processor Memory Map Addresses
Memory Range
–
0xFFE00000 0xFFFFFFFF
–
0xFFC00000 0xFFDFFFFF
–
0xFFB00000 0xFFB00FFF
–
0xFFA00000 0xFFA03FFF
–
0xFF900000 0xFF903FFF
–
0xFF800000 0xFF803FFF
–
0xF0040000 0xFF7FFFFF
–
0xF0000000 0xF003FFFF
–
0xEF000400 0xEFFFFFFF
–
0xEF000000 0xEF0003FF
–
0x00000000 0xEEFFFFFF
The section in
MEMORY
L2 SRAMs are available and that L1 is unused. Refer to the VisualDSP++
C/C++ Compiler and Library Manual for Blackfin Processors and the appro-
priate Hardware Reference for information about cache configuration.
See the Memory chapter in an appropriate Hardware Reference for
information about your target processor's memory organization.
2-14
Table 2-1. Address ranges that are not listed
Range Description
Core MMR registers (2MB)
System MMR registers (2MB)
Scratchpad SRAM (4K)
Instruction SRAM (16K)
Data Memory Bank 2 SRAM (16K)
Data Memory Bank 1 SRAM (16K)
Reserved
L2 Memory Bank SRAM (256K)
Reserved
Boot ROM (1K)
External memory
Listing 2-1 on page 2-24
VisualDSP++ 3.5 Linker and Utilities Manual
assumes that only L1 and
for 16-Bit Processors