Adsp-Bf535 Processor Memory Architecture Overview - Analog Devices VisualDSP++ 3.5 Manual

Link Target Description
• Memory Characteristics. List the types of memory in your DSP
system and the address ranges and word width associated with each
memory type. Memory type is defined as
• MEMORY{} Command. Construct a
bine the information from the previous two lists and to declare
your system's memory segments.
For complete information, refer to

ADSP-BF535 Processor Memory Architecture Overview

As an example, this section describes the Blackfin ADSP-BF535 memory
architecture and memory map organization.
Other processors in the Blackfin family (ADSP-BF531/2/3 and
ADSP-561) have very different memory architectures. Refer to
Hardware Reference manuals of target processors for appropriate
information.
The ADSP-BF535 processor includes the L1 memory subsystem with a
16Kbyte instruction SRAM/cache, a dedicated 4Kbyte data scratchpad,
and a 32Kbyte data SRAM/cache configured as two independent 16Kbyte
banks (memories). Each independent bank can be configured as SRAM or
cache.
The ADSP-BF535 processor also has an L2 SRAM memory that provides
2 Mbits (256 Kbytes) of memory. The L2 memory is unified; that is, it is
directly accessible by the instruction and data ports of the ADSP-BF535
processor. The L2 memory is organized as a multi-bank architecture of
single-ported SRAMs (there are eight sub-banks in L2), such that simulta-
neous accesses by the core and the DMA controller to different banks can
occur in parallel.
Figure 2-5 shows the ADSP-BF535 system block diagram.
2-12
MEMORY{}
"MEMORY{}" on page
VisualDSP++ 3.5 Linker and Utilities Manual
or .
RAM ROM
command to com-
3-29.
for 16-Bit Processors