Overview
Overview
Current Analog Devices processors use fast Harvard memory architecture
that has separate program and data memories. This memory architecture
improves processing speed because the machine can fetch program
instructions and data in parallel. A data fetch from memory can thus be
accomplished in a single memory cycle. Analog Devices DSPs possess a
separate program and data memory for speed. For extra speed, data can be
kept in program memory as well as in data memory, and there are instruc-
tions to fetch data from both memories simultaneously.
To use the full memory bandwidth, Blackfin and ADSP-219x processors
possess an instruction cache. Instructions which come from cache memory
free up the program memory bus for data access fetch from program mem-
ory. This feature permits multiply accumulate instructions to fetch a
multiplier and a multiplicand, compute a product, and add the new prod-
uct to the accumulator, all in a single instruction. In this case, it is
important to locate the multiplier data in program memory and the multi-
plicand data in data memory. It is the programmer's responsibility to
assign data buffers to memory. This is done with instructions to the
linker. In addition, each DSP project must fit into a different memory
arrangement. Different DSP boards have different amounts of memory,
located at different addresses.
For example, the ADSP 2181 DSP has the ability to access up to two 8
Kbyte pages of external overlay memory for both program memory and
data memory. The DSP still contains 16 Kbyte of program memory and
data memory but can access up to another 16 Kbyte of program memory
and another 16 Kbyte of data memory.
Blackfin processors have an integrated instruction and data cache, which
can be used to reduce the manual process of moving instructions and data
in and out of core. Memory overlays can also be used to run an application
efficiently, but they require a user-managed set of DMAs. Since Blackfin
5-2
VisualDSP++ 3.5 Linker and Utilities Manual
for 16-Bit Processors
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