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System MMU
1.4.3.1.2.5 First-Level Section Descriptor Format
Each section descriptor in the first-level translation table specifies the complete translation properties for a
1MB section or a 16MB supersection.
NOTE: Supersection descriptors must be repeated 16 times, because each descriptor in the
first-level translation table describes 1MB of memory. If an access points to a descriptor that
is not initialized, the MMU will behave in an unpredictable way.
In addition to the address translation itself, three parameters are specified in the section descriptors:
•
Endianness - The endianness parameter specifies whether the memory section uses a big- or
little-endian data format. This parameter is locked to little endian.
•
Element Size - The element size parameter can optionally specify the data access size (8, 16, or 32
bits) for all data items in the defined section.
•
Mixed Region - The mixed region parameter specifies whether the information about the data access
size is detected from the access itself (access-based detection) or if the specified element size
parameter is used (page-based detection). For example, the specified element size parameter can be
used when several smaller sized accesses are packed into a bigger sized access, such as two 16-bit
accesses packed into one 32-bit access. In this case, with no specified data access size, 32 bits would
be the access size detected, leading to an incorrect result. To avoid this problem, specify the data
access size for the memory section.
1.4.3.1.2.6 Section Translation Summary
Sections and supersections can be translated based solely on the information in the first-level translation
table.
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First-level TranslationTable
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Chip Level Resources
Preliminary
Figure 1-17. Section Translation Summary
Virtual Address
Section Base Address
(From First-level Descriptor)
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