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System MMU
L3 Interconnect configuration port: Accesses to undecoded register addresses must not give an error
response.
To protect against changes to the address translation between a READEX and the corresponding write or
during a burst the following configuration operations are protected against writes during these processes:
1. TLB update
2. Global flush
3. Flush entry
4. MMU disable
The protection is implemented by stalling the configuration interconnect transaction until the write can
proceed safely.
1.4.4 MMU Low-level Programming Models
This section covers the low-level hardware programming sequences for configuration and usage of the
module.
1.4.4.1
MMU Global Initialization
1.4.4.1.1 Main Sequence - MMU Global Initialization
The System MMU can be enabled or disabled in MMU_CFG register (refer Control Module chapter).
Figure 1-24
shows the procedure to initialize the MMU after a power-on or software reset.
MMU_LD_TLB[0] LDTLBITEM = 0x1
Lock TLB
MMU_LOCK = 0x-
Disable walking logic
MMU_CNTL[0] TWLENABLE = 0x0
Enable
MMU_CNTL
130
Chip Level Resources
Figure 1-24. MMU Global Initialization
Start
Use
Yes
translation
tables?
No
Write
TLB entries
entries
MMU_CNTL[0] TWLENABLE = 0x1
MMU
[1] MMUENABLE = 0x1
End
© 2011, Texas Instruments Incorporated
Preliminary
Write
translation
tables
Time-
Yes
critical
entries?
No
MMU_LD_TLB[0] LDTLBITEM
Enable walking logic
www.ti.com
Write TLB entries
Lock TLB entries
MMU_LOCK = 0x-
SPRUGX9 – 15 April 2011
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