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System MMU
1.4.5.2.4 MMU_IRQSTATUS
The MMU_IRQSTATUS register is shown in
31
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-5
Reserved
4
MULTIHITFAULT
3
TABLEWALKFAULT
2
EMUMISS
1
TRANSLATIONFAUL
T
0
TLBMISS
136
Chip Level Resources
Preliminary
Figure 1-28
Figure 1-28. MMU_IRQSTATUS
Reserved
R-0
5
4
MULTIHITFAU
LT
R/W-0
Table 1-26. MMU_IRQSTATUS Field Descriptions
Value
Description
0
Write 0's for future compatibility read returns 0.
1-0
Error due to multiple matches in the TLB.
Read 0x0: MultiHitFault false.
Write 0x0: MultiHitFault status bit unchanged.
Write 0x1: MultiHitFault status bit is reset.
Read 0x1: MultiHitFault is true ("pending").
1-0
Error response received during a Table Walk.
Read 0x0: TableWalkFault false.
Write 0x0: TableWalkFault status bit unchanged.
Write 0x1: TableWalkFault status bit is reset.
Read 0x1: TableWalkFault is true ("pending").
1-0
Unrecoverable TLB miss during debug (hardware TWL disabled).
Read 0x0: EMUMiss false.
Write 0x0: EMUMiss status bit unchanged.
Write 0x1: EMUMiss status bit is reset.
Read 0x1: EMUMiss is true ("pending").
1-0
Invalid descriptor in translation tables (translation fault).
Read 0x0: TranslationFault false.
Write 0x0: TranslationFault status bit unchanged.
Write 0x1: TranslationFault status bit is reset.
Read 0x1: TranslationFault is true ("pending").
1-0
Unrecoverable TLB miss (hardware TWL disabled).
Read 0x0: TLBMiss false.
Write 0x0: TLBMiss status bit unchanged.
Write 0x1: TLBMiss status bit is reset.
Read 0x1: TLBMiss is true ("pending").
© 2011, Texas Instruments Incorporated
and described in
Table
3
2
TABLEWALKF
EMUMISS
AULT
R/W-0
R/W-0
www.ti.com
1-26.
16
1
0
TRANSLATION
TLBMISS
FAULT
R/W-0
R/W-0
SPRUGX9 – 15 April 2011
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