Mmu_Sysconfig Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

System MMU
1.4.5.2.2 MMU_SYSCONFIG
The MMU_SYSCONFIG register is shown in
31
15 10
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-10 Reserved
9-8 CLOCKACTIVITY
7-5 Reserved
4-3 IDLEMODE
2 Reserved
1 SOFTRESET
0 AUTOIDLE
134
Chip Level Resources
Preliminary
Figure 1-26
Figure 1-26. MMU_SYSCONFIG
Reserved
9 8 7 5
CLOCKACTIVI Reserved
TY
R/W-0 R-0
Table 1-24. MMU_SYSCONFIG Field Descriptions
Value Description
0 Write 0's for future compatibility. Reads returns 0.
0 Clock activity during wake-up mode 00 Functional and Interconnect clocks can be switched
off.
0 Write 0's for future compatibility. Reads returns 0
Idle Mode
0 Force-idle. An idle request is acknowledged unconditionally.
1h No-idle. An idle request is never acknowledged.
2h Smart-idle. Acknowledgment to an idle request is given based on the internal activity of the
module.
3h Reserved do not use.
0 Write 0's for future compatibility. Reads returns 0.
1-0 Software reset. This bit is automatically reset by the hardware. During reads, it always return
0.
Read 0x0: always return 0
Write 0x0: no functional effect
Write 0x1: The module is reset
Read 0x1: never happens
Internal interconnect clock gating strategy.
0 Interconnect clock is free-running.
1 Automatic interconnect clock gating strategy is applied, based on the interconnect interface
activity.
© 2011, Texas Instruments Incorporated
and described in
R-0
4 3 2
IDLEMODE Reserved
R/W-0 R-0
www.ti.com
Table 1-24.
1 0
SOFTRESET AUTOIDLE
R/W-0 R/W-0
SPRUGX9 – 15 April 2011
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