1.5.3 Sgx Functional Description; Sgx Block Diagram - Texas Instruments TMS320C6A816 Series Technical Reference Manual

SGX530 Graphics Subsystem

1.5.3 SGX Functional Description

1.5.3.1

SGX Block Diagram

The SGX subsystem is based on the POWERVR® SGX530 core from Imagination Technologies. The
architecture uses programmable and hard coded pipelines to perform various processing tasks required in
2D, 3D, and video processing. The SGX architecture comprises the following elements:
• Coarse grain scheduler
– Programmable data sequencer (PDS)
– Data master selector (DMS)
• Vertex data master (VDM)
• Pixel data master (PDM)
• General-purpose data master
• USSE
• Tiling coprocessor
• Pixel coprocessor
• Texturing coprocessor
• Multilevel cache
Figure 1-46 shows a block diagram of the SGX cores.
POWERVR
SGX530
Power
management
control
register
block
SOCIF
L3 interconnect
150
Chip Level Resources
Preliminary
Figure 1-46. SGX Block Diagram
Vertex data Coarse-grain
master scheduler
Prog. data
Pixel data
sequencer
master
Data master
General-purpose selector
data master
Texturing coprocessor
MMU
BIF
L3 interconnect
© 2011, Texas Instruments Incorporated
Tiling
coprocessor
Universal
scalable
shader
engine
(USSE)
Pixel
coprocessor
Multilevel cache
sgx-003
SPRUGX9 – 15 April 2011
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