Interrupt Events Register (Ocp_Interrupt_Event) - Texas Instruments TMS320C6A816 Series Technical Reference Manual

SGX530 Graphics Subsystem

1.5.4.1.17 Interrupt Events Register (OCP_INTERRUPT_EVENT)

The Interrupt Events Register (OCP_INTERRUPT_EVENT) is shown in
Table 1-60.
Figure 1-63. Interrupt Events Register (OCP_INTERRUPT_EVENT)
31
15
7 6
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-60. Interrupt Events Register (OCP_INTERRUPT_EVENT) Field Descriptions
Bit Field
31-11 Reserved
10 TARGET_INVALID_OCP_CMD
9 TARGET_CMD_FIFO_FULL
7-6 Reserved
5 INIT_MEM_REQ_FIFO_OVERRUN
4 INIT_READ_TAG_FIFO_OVERRUN
3 INIT_PAGE_CROSS_ERROR
162
Chip Level Resources
Preliminary
Reserved
Reserved
R-0
5 4
INIT_MEM_RE INIT_READ_TA
Q_FIFO_OVER G_FIFO_OVER ROSS_ERROR
RUN RUN
R/W-0 R/W-0
Value Description
0 Reserved.
Invalid command from OCP
0 Read: No event pending.
1 Read: Event pending.
0 Write: Clear the event.
1 Write: Set event and interrupt if enabled (debug only).
Command FIFO full.
0 Read: No event pending.
1 Read: Event pending.
0 Write: Clear the event.
1 Write: Set event and interrupt if enabled (debug only).
0 Reserved.
Memory request FIFO overrun.
0 Read: No event pending.
1 Read: Event pending.
0 Write: Clear the event.
1 Write: Set event and interrupt if enabled (debug only).
Read tag FIFO overrun.
0 Read: No event pending.
1 Read: Event pending.
0 Write: Clear the event.
1 Write: Set event and interrupt if enabled (debug only).
Memory page had been crossed during a burst.
0 Read: No event pending.
1 Read: Event pending.
0 Write: Clear the event.
1 Write: Set event and interrupt if enabled (debug only).
© 2011, Texas Instruments Incorporated
Figure 1-63
R-0
11 10
TARGET_INVA TARGET_CMD
LID_OCP_CMD
R/W-0
3 2
INIT_PAGE_C INIT_RESP_ER
ROR
R/W-0 R/W-0
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and described in
16
9 8
TARGET_RES
_FIFO_FULL P_FIFO_FULL
R/W-0 R/W-0
1 0
INIT_RESP_U INIT_RESP_U
NUSED_TAG NEXPECTED
R/W-0 R/W-0
SPRUGX9 – 15 April 2011
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