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CLKIN1
MAIN PLL
L4 interconnect
SerDes PLL
SERDES_CLKPIN
DDRPLL
VIDEOPLL
AUDIOPLL
SPRUGX9 – 15 April 2011
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Preliminary
Figure 1-67. Detailed Clock Architecture
SYSCLK1
DSPSS
SYSCLK2
MIPUSS
SYSCLK4
L3 INTERCONNECT
HDVPSS
EDMA
SYSTEM MMU
EMAC
OCMC RAM
PCIE
SATA
SYSCLK23
SGX530
VTP
DMM
DDR2/3
SYSCLK11
SYSCLK17
SYSCLK15
HDVPSS
SYSCLK13
SYSCLK18
SYSCLK20, SYSCLK21, SYSCLK22
© 2011, Texas Instruments Incorporated
Device Clocking and Flying Adder PLL
UART
I2C
SPI
SD/SDIO
TIMER
GPIO
GPMC
WDT
MAILBOX
SPINLOCK
USB
McASP
McBSP
RTC
ELM
SMART REFLEX
Chip Level Resources
185
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