Table of Contents
Advertisement
System MMU
1.4.3.1.2.8 Two-Level Translation
Two-level translation is used when fine-grain granularity is required, that is, when memory sections
smaller than 1MB are needed. In this case, the first-level descriptor provides a pointer to the base address
of a second-level translation table. This second-level table is indexed by bits 19 to 12 of the virtual
address.
31
First-level translation table
Each second-level translation table describes the translation of 1MB of address space in pages of 64KB
(large page) or 4KB (small page). It consists of 256 second-level descriptors describing 4KB each.
NOTE: In the case of a large page, the same descriptor must be repeated 16 times. If an access
points to a descriptor that is not initialized, the MMU will behave in an unpredictable way."
124
Chip Level Resources
Preliminary
Figure 1-19. Two-Level Translation
Virtual address
20 19
12 11
First-level descriptor
© 2011, Texas Instruments Incorporated
0
Second-level translation table
www.ti.com
Second-level descriptor
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
