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1.10.3 Flying Adder PLL
The device uses Flying Adder PLLs for all on-chip PLLs.
Adder PLL.
Flying Adder PLL (FAPLL) has two main components:
1. Multiphase PLL
2. Flying Adder Synthesizer.
The multiphase PLL takes input reference clock (f
output to the flying adder synthesizer. The flying adder synthesizer takes this multi phase clock input and
produces a variable frequency clock (f
out clock f
.
o
The f
frequency of the PLL is given by
vco
f
= (N/P) x f
vco
r
The f
frequency of the FAPLL is givey by
s
f
= (
x K)/FREQ
s
fvco
The f
frequency of the Post divider is given by
o
f
= f
/M
o
s
Where:
f
= VCO frequency. Range is 800-1850 MHz.
vco
f
= Input reference frequency
r
N = Multiplier
P = Pre-divider
K = Phase Output. 8 is the value for this device
f
= FAPLL output
s
f
= Post Divider output
o
FREQ = 4 bits integer and 24 bits of fractional value
M = Post Divider. Value ranges from 1 to 255.
There can be multiple flying adder synthesizers attached to one multi phase PLL to generate different
frequencies. FREQ and M values can be adjusted for each clock separately based on the frequency
needed.
1.10.3.1 PLL Types
This device has 4 on-chip PLLs and they are as follows:
1. MAIN PLL
2. DDR PLL
3. VIDEO PLL
SPRUGX9 – 15 April 2011
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Preliminary
Figure 1-68. Flying Adder PLL
FREQ
fp
fr
/P
PFD
C.P.
/N
). There is post divider on this clock that takes in clock f
s
© 2011, Texas Instruments Incorporated
Device Clocking and Flying Adder PLL
Figure 1-68
shows basic structure of the Flying
fs
Flying-adder
/M
synthesizer
K
fvco
VCO
), mutliplies it with factor N and provides a K phase
r
fo
and drives
s
Chip Level Resources
187
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