Table 3-20 Ipcmpcellid1 Register Bit Assignments; Table 3-21 Ipcmpcellid2 Register Bit Assignments; Table 3-22 Ipcmpcellid3 Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

ARM DDI 0306B
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PrimeCell Identification Register 1
The hard-coded IPCMPCellID1 Register defines the reset value. Table 3-20 lists the bit
assignments for the IPCMPCellID1 Register.
PrimeCell Identification Register 2
The hard-coded IPCMPCellID2 Register defines the reset value. Table 3-21 lists the bit
assignments for the IPCMPCellID2 Register.
PrimeCell Identification Register 3
The hard-coded IPCMPCellID3 Register defines the reset value. Table 3-22 lists the bit
assignments for the IPCMPCellID3 Register.
Copyright © 2003, 2004. ARM Limited. All rights reserved.

Table 3-20 IPCMPCellID1 Register bit assignments

Bits Name
[31:8] -
[7:0] IPCMPCellID1

Table 3-21 IPCMPCellID2 Register bit assignments

Bits Name
[31:8] -
[7:0] IPCMPCellID2

Table 3-22 IPCMPCellID3 Register bit assignments

Bits Name
[31:8] -
[7:0] IPCMPCellID3
Programmer's Model
Description
Read undefined
These bits read back as
0xF0
Description
Read undefined
These bits read back as
0x05
Description
Read undefined
These bits read back as
0xB1
3-23