ARM PrimeCelL PL320 Technical Reference Manual page 5

List of Tables
PrimeCell Inter-Processor Communications
Module (PL320) Technical Reference Manual
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 3-11
Table 3-12
Table 3-13
Table 3-14
Table 3-15
Table 3-16
ARM DDI 0306B
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Change history .............................................................................................................. ii
Channel ID to interrupt mapping ............................................................................... 2-6
Configuring number of mailboxes ........................................................................... 2-12
Configuring number of interrupts ............................................................................. 2-14
Configuring number of data registers ...................................................................... 2-16
IPCM register summary ............................................................................................ 3-6
IPCMxSOURCE Register bit assignments .............................................................. 3-12
IPCMxDSET Register bit assignments ................................................................... 3-12
IPCMxDCLEAR Register bit assignments ............................................................... 3-13
IPCMxDSTATUS Register bit assignments ............................................................ 3-13
IPCMxMODE Register bit assignments .................................................................. 3-14
IPCMxMSET Register bit assignments ................................................................... 3-15
IPCMxMCLEAR Register bit assignments .............................................................. 3-15
IPCMxMSTATUS Register bit assignments ............................................................ 3-16
IPCMxSEND Register bit assignments ................................................................... 3-17
IPCMxDR0-6 Register bit assignments ................................................................... 3-17
IPCMMISx Register bit assignments ....................................................................... 3-18
IPCMRISx Register bit assignments ....................................................................... 3-18
IPCMCFGSTAT Register bit assignments .............................................................. 3-19
IPCMPeriphID0 Register bit assignments ............................................................... 3-20
IPCMPeriphID1 Register bit assignments ............................................................... 3-21
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