Table 3-10 Ipcmxsend Register Bit Assignments; Table 3-11 Ipcmxdr0-6 Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

3.3.10 Mailbox Data Registers
3.3.11 Masked Interrupt Status Registers
ARM DDI 0306B
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Table 3-10 lists the register bit assignments.
The read/write IPCMxDR0-6 Registers hold the message. The Mailbox Data Registers
can only be written to after the Mailbox Source Register is defined and are cleared when
the Mailbox Source Register is cleared.
Table 3-11 lists the register bit assignments.
The read-only IPCMMISx Registers contain the current mailbox status for every
interrupt identified by the address encoding. This enables each core to read a single
register to determine which mailbox caused the interrupt. For example, if Core0 is
mapped to Channel ID0, it reads IPCMMIS0 to determine which mailboxes require
attention.
Figure 3-6 on page 3-18 shows how Mailbox0 status is presented to Core0 through the
use of two status registers, IPCMMIS0 and IPCMRIS0.
Copyright © 2003, 2004. ARM Limited. All rights reserved.

Table 3-10 IPCMxSEND Register bit assignments

Bit Name Function
[31:2] - Read undefined. Write as zero.
[1:0] Send Send message: 00 = inactive 01 = send
message to destination core(s) 10 = send
message to source core 11 = invalid,
unpredictable behavior

Table 3-11 IPCMxDR0-6 Register bit assignments

Programmer's Model
Bit Name Function
[31:0] Data Message data
3-17