Figure 3-2 Mailbox0 Register Map; Figure 3-3 Interrupt0 Register Map - ARM PrimeCelL PL320 Technical Reference Manual

ARM DDI 0306B
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Figure 3-3 shows the register map for each Interrupt0.
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Programmer's Model
Mailbox Data Register 6
Mailbox Data Register 5
Mailbox Data Register 4
Mailbox Data Register 3
Mailbox Data Register 2
Mailbox Data Register 1
Mailbox Data Register 0
Mailbox Send Registers
Mailbox Mask Status Registers
Mailbox Mask Clear Registers
Mailbox Mask Set Registers
Mailbox Mode Registers
Mailbox Destination Status Registers
Mailbox Destination Clear Registers
Mailbox Destination Set Registers
Mailbox Source Registers

Figure 3-2 Mailbox0 register map

Raw Interrupt Status Registers
Masked Interrupt Status Registers

Figure 3-3 Interrupt0 register map

0x03C
0x038
0x034
0x030
0x02C
0x028
0x024
0x020
0x01C
0x018
0x014
0x010
0x00C
0x008
0x004
0x000
0x804
0x800
3-5