ARM PrimeCelL PL320 Technical Reference Manual page 57

Name
-
IPCMTCR
IPCMTOR
-
IPCMPeriphID0
IPCMPeriphID1
IPCMPeriphID2
IPCMPeriphID3
IPCMPCellID0
IPCMPCellID1
IPCMPCellID2
IPCMPCellID3
ARM DDI 0306B
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Base Reset
Type
offset value
0x904-0xE - -
FC
RW
0xF00 0x0
0xF04 RW 0x00000000
0xF08-0xF - -
DF
0xFE0 RO 0x20
RO
0xFE4 0x13
0xFE8 RO 0x04
0x00
RO
0xFEC
0xFF0 RO 0x0D
RO
0xFF4 0xF0
RO
0xFF8 0x05
RO
0xFFC 0xB1
Copyright © 2003, 2004. ARM Limited. All rights reserved.
Table 3-1 IPCM register summary (continued)
Description
Reserved
See Integration Test Control Register on page 4-3
See Integration Test Output Register on page 4-3
Reserved
See Peripheral Identification Register 0 on page 3-20
See Peripheral Identification Register 1 on page 3-21
See Peripheral Identification Register 2 on page 3-21
See Peripheral Identification Register 3 on page 3-21
See PrimeCell Identification Register 0 on page 3-22
See PrimeCell Identification Register 1 on page 3-23
See PrimeCell Identification Register 2 on page 3-23
See PrimeCell Identification Register 3 on page 3-23
Programmer's Model
3-11