ARM PrimeCelL PL320 Technical Reference Manual page 56

Programmer's Model
Name
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IPCMCFGSTAT
3-10
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Base Reset
Type
offset value
0x888-0x8 - -
8C
0x890-0x8 - -
94
0x898-0x8 - -
9C
0x8A0-0x8 - -
A4
0x8A8-0x8 - -
AC
0x8B0-0x8 - -
B4
0x8B8-0x8 - -
BC
0x8C0-0x8 - -
C4
0x8C8-0x8 - -
CC
0x8D0-0x8 - -
D4
0x8D8-0x8 - -
DC
0x8E0-0x8 - -
E4
0x8E8-0x8 - -
EC
0x8F0-0x8 - -
F4
0x8F8-0x8 - -
FC
RO -
0x900
Copyright © 2003, 2004. ARM Limited. All rights reserved.
Table 3-1 IPCM register summary (continued)
Description
Reserved for Interrupt17
Reserved for Interrupt18
Reserved for Interrupt19
Reserved for Interrupt20
Reserved for Interrupt21
Reserved for Interrupt22
Reserved for Interrupt23
Reserved for Interrupt24
Reserved for Interrupt25
Reserved for Interrupt26
Reserved for Interrupt27
Reserved for Interrupt28
Reserved for Interrupt29
Reserved for Interrupt30
Reserved for Interrupt31
See Configuration Status Register on page 3-18
ARM DDI 0306B