Figure 2-11 Configuration, Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1
ARM DDI 0306B
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A HB bus
Figure 2-12 shows the messaging sequence.
IPCM0SOURCE[1:0]
IPCM0DSTATUS[1:0]
IPCM0MODE[1:0]
IPCM0MSTATUS[1:0]
IPCM0SEND[1:0]
IPCM0DR0[31:0]
IPCM1SOURCE[1:0]
IPCM1DSTATUS[1:0]
IPCM1MODE[1:0]
IPCM1MSTATUS[1:0]
IPCM1SEND[1:0]
IPCM1DR0[31:0]
IPCMRIS0[3:0]
IPCMRIS1[3:0]
IPCMINT[3:0]
Figure 2-12 Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1
Copyright © 2003, 2004. ARM Limited. All rights reserved.
IPCM INT[0]
Interrupt
controller0
Core0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0
0
0
0
0
00000000
0
0
0
0
00000000
0
0
0
Functional Overview
IPCM INT[1]
IPCM
Interrupt
controller1
Minimum
conf iguration:
M BOXNUM =4
INTNUM =2
Core1
DATANUM =1
15
16 17 18
19 20 21
1
2
2
3
1
2
0
DA7A0000
1
2
0
3
1
2
DA7A1111
2
1
0
2
0
2
0
2
1
0
0
0
2-25