ARM PrimeCelL PL320 Technical Reference Manual page 26

Inter-processor communications module

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Functional Overview

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Defining source core

A core must obtain a mailbox to send a message. To do this the core writes one of its

Channel IDs to the Mailbox Source Register and then reads the Mailbox Source

software must ensure that only a one-hot encoded number is written to the Mailbox

Source Register. You can only clear the Mailbox Source Register after it is programmed.

Any writes other than

0x00000000

single core has control of the mailbox at any one time.

A core gives up a mailbox, when it is no longer required, by clearing the Mailbox

Source Register. Clearing the Mailbox Source Register also clears all the other registers

in the mailbox. This guarantees that a mailbox is always cleared when it is newly

allocated.

Defining destination core

The Mailbox Destination Register has separate Set and Clear write locations to enable

you to set individual bits in the Mailbox Destination Register without using

read-modify-write transfers. You can set a single bit in the Mailbox Destination Register

by writing that bit to the Destination Set Register. This causes the hardware to OR that

bit with the current Mailbox Destination Register value. Similarly, you can clear a

single bit in the Mailbox Destination Register by writing that bit to the Destination Clear

When the source core defines the mode of a mailbox, it defines which other cores are to

receive the message by programming the OR of all the Channel IDs into the Mailbox

Destination Register. If a core has more than one Channel ID only one is used per

message. You can only write to the Mailbox Destination Register after the Mailbox

Source Register is defined.

Using the Mailbox Mask Register

The Mailbox Mask Register uses separate Set and Clear registers for modification

similar to the Mailbox Destination Register. The Mailbox Mask Register enables the

interrupt outputs. To enable interrupts for a particular mailbox, a core writes its Channel

ID to the Mask Set location. The interrupt for that mailbox can be masked out by writing

the same Channel ID to the Mask Clear location. You can only write to the Mailbox

Mask Register locations after the Mailbox Source Register is defined.

are ignored. This mechanism guarantees that only a

ARM DDI 0306B

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