ARM PrimeCelL PL320 Technical Reference Manual page 27

Inter-processor communications module

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Using the Mailbox Send Register

A message is sent by setting bit 0 of the Mailbox Send Register. This triggers the

interrupt to the destination core. Clearing this bit clears the interrupt to the destination

core. The acknowledge message is sent to the source core by setting bit 1 of the Mailbox

Send Register. Clearing this bit clears the interrupt to the source core. You can use one

write to clear bit 0 and set bit 1 in the Mailbox Send Register, although this is not

mandatory. You cannot set bit 1 then clear bit 0 because 11 is an invalid value for the

Mailbox Send Register. The Mailbox Send Register can only be written to after the

Mailbox Source Register is defined.

Mailbox Data Registers

The Mailbox Data Registers are general-purpose 32-bit registers that contain the

message and can only be written to after the Mailbox Source Register is defined. The

Mailbox Data Registers are normally written to before sending the message.

Setting mode

The Mailbox Mode Register controls how the acknowledge interrupt is sent back to the

source core, and whether the current mailbox is linked to the next mailbox in the IPCM.

The Mailbox Mode Register has two bits and you can only write to it after the Mailbox

Source Register is defined.

Auto Acknowledge

In Auto Acknowledge mode, an acknowledge interrupt is automatically sent to the

source core after the final destination core has cleared its interrupt. Destination cores

must clear their interrupts by writing their Channel ID value to the Destination Clear

location. This clears their Channel ID from the Mailbox Destination Register. When the

Mailbox Destination Register finally reaches zero, indicating that all destination cores

have cleared their interrupts, the mailbox automatically detects this, clears bit 0 and sets

bit 1 of the Mailbox Send Register. The source core then receives the acknowledge

interrupt. The data associated with an Auto Acknowledge is the same as that for the

original message. You can use Auto Acknowledge mode for 1-32 destination cores.

Note

You can use Auto Acknowledge when the system contains just two cores, a source core

and a destination core.

When Auto Acknowledge mode is disabled, the acknowledge interrupt is optional. The

destination core must clear its interrupt by clearing bit 0 of the Mailbox Send Register.

Only when the destination core sets bit 1 of the Mailbox Send Register does the source

Functional Overview

2-9

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