Table 3-7 Ipcmxmset Register Bit Assignments; Table 3-8 Ipcmxmclear Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

3.3.7 Mailbox Mask Clear Registers
3.3.8 Mailbox Mask Status Registers
ARM DDI 0306B
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Table 3-7 lists the register bit assignments.
Bit
[31:0]
The write-only IPCMxMCLEAR Registers clear bits in the Mailbox Mask Registers.
They can only be written to after the Mailbox Source Register is defined.
Table 3-8 lists the register bit assignments.
Bit
[31:0]
The read-only IPCMxMSTATUS Registers contain the current status of the Mailbox
Mask Registers. Each core is assigned its own bit.
When set, the Mailbox Mask Registers enable the interrupts to each core through
bit-wise encoding for each of the Channel IDs. These bits reset to 0, disabling the
interrupts.
When cleared, the Mailbox Mask Registers disable the interrupts, enabling the cores to
use polling rather than interrupts for messaging.
The Mailbox Mask Registers are all cleared when the Mailbox Source Register is
cleared.
Copyright © 2003, 2004. ARM Limited. All rights reserved.

Table 3-7 IPCMxMSET Register bit assignments

Name Function
Mask Set Used to set bits in the Mailbox Mask Register

Table 3-8 IPCMxMCLEAR Register bit assignments

Name Function
Mask Clear Used to clear bits in the Mailbox Mask Register
Programmer's Model
3-15