ARM PrimeCelL PL320 Technical Reference Manual page 28

Inter-processor communications module

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Functional Overview

2-10

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core obtain its acknowledge interrupt, indicating that the destination core has finished

with the message. You can only disable Auto Acknowledge mode when there is only

one destination core, where there is also a possibility of updating the message for the

acknowledge.

Auto Link

Auto Link provides a mechanism to link mailboxes together so that when a message is

acknowledged in one mailbox, the next message is sent from the linked mailbox instead

of interrupting the source core. When Auto Link is enabled, the destination core clears

bit 0 and sets bit 1 of the Mailbox Send Register in the usual way, but the acknowledge

interrupt to the source core is masked out and Mailbox Send Register bit 0 is set in the

next mailbox, sending that message.

In this mode, a source core can allocate multiple mailboxes to itself, link them together

by setting the Auto Link bits and preload messages in all the mailboxes. When the first

message is sent, it is not acknowledged until all the messages have been sent. There is

no restriction on the destinations of these messages or whether Auto Acknowledge is

enabled when Auto Link is used. In the IPCM, Mailbox0 can be linked to Mailbox1,

which in turn can be linked to Mailbox2, up to Mailbox31. For example, if you want to

link Mailbox0, Mailbox1, and Mailbox2, set the Auto Link bits in Mailbox0 and

Mailbox1. Do not set the Auto Link bit in Mailbox2, to enable the acknowledge

interrupt to be sent back to the source core.

When Auto Link is disabled, the source core is interrupted if an acknowledge interrupt

is sent that has no effect on any other mailbox.

Note

When using Auto Link with Auto Acknowledge, the mailbox automatically sets

Mailbox Send Register bit 1 in the first mailbox to send the acknowledge back to the

source core but, because Auto Link is also set, the mailbox automatically sets Mailbox

Send Register bit 0 in the linked mailbox.

Interrupts and status Registers

When a core receives an IPCM interrupt, it determines which mailbox triggered it by

reading the Masked Interrupt Status Register related to that interrupt line. Each Masked

Interrupt Status Register contains up to 32 bits, each bit referring to a single mailbox.

If a core is using a mailbox in polled mode, it can use the Raw Interrupt Status Register

to indicate which mailbox requires attention.

ARM DDI 0306B

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