Test Registers; Table 4-1 Ipcmtcr Register Bit Assignments; Table 4-2 Ipcmtor Register Bit Assignments; Figure 4-1 Ipcmtcr Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

4.2

Test registers

4.2.1 Integration Test Control Register
4.2.2 Integration Test Output Register
ARM DDI 0306B
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The input configuration pin INTNUM defines the bit width of the IPCMTOR register.
For example, when INTNUM is set to 1, IPCMTOR is only a single bit wide (bit 0).
Setting INTNUM to 32 sets IPCMTOR to 32 bits wide.
The IPCM test registers are memory-mapped as shown in IPCM register map on
page 3-4 and Table 3-1 on page 3-6. The address offset is from the base address.
The read/write IPCMTCR Register controls the IPCM integration test mode. When
ITEN=1, the IPCM is placed in integration test mode. Figure 4-1 shows and Table 4-1
lists the register bit assignments.
31
The read/write IPCMTOR Register enables the output port signals of the IPCM to be
driven directly rather than from their normal internal logic source when in integration
test mode, that is, when ITEN=1 in the IPCMTCR Register. Table 4-2 lists the register
bit assignments.
Copyright © 2003, 2004. ARM Limited. All rights reserved.
Undefined

Figure 4-1 IPCMTCR Register bit assignments

Table 4-1 IPCMTCR Register bit assignments

Bit Name Function
[31:1] - Read undefined. Write as zero.
[0] ITEN Integration test enable: 0 =
integration test mode disabled 1 =
integration test mode enabled.

Table 4-2 IPCMTOR Register bit assignments

Bit Name
[31:0] IntTest
Programmer's Model for Test
1 0
ITEN
Function
IPCMINT[31:0] output
4-3