Table 3-16 Ipcmperiphid1 Register Bit Assignments; Table 3-17 Ipcmperiphid2 Register Bit Assignments; Table 3-18 Ipcmperiphid3 Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

ARM DDI 0306B
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Peripheral Identification Register 1
The hard-coded IPCMPeriphID1 Register defines the reset value. Table 3-16 lists the bit
assignments for the IPCMPeriphID1 Register.
Peripheral Identification Register 2
The hard-coded IPCMPeriphID2 Register defines the reset value. Table 3-17 lists the bit
assignments for the IPCMPeriphID2 Register.
Peripheral Identification Register 3
The hard-coded IPCMDPeriphID3 Register defines the reset value. Table 3-18 lists the
bit assignments for the IPCMPeriphID3 Register.
Copyright © 2003, 2004. ARM Limited. All rights reserved.

Table 3-16 IPCMPeriphID1 Register bit assignments

Bits Name
[31:8] -
[7:4] Designer0
[3:0] PartNumber1

Table 3-17 IPCMPeriphID2 Register bit assignments

Bits Name
[31:8] -
[7:4] Revision
[3:0] Designer1

Table 3-18 IPCMPeriphID3 Register bit assignments

Bits Name
[31:8] -
[7:0] Configuration
Programmer's Model
Description
Read undefined
These bits read back as
0x1
These bits read back as
0x3
Description
Read undefined
These bits read back as
0x0
These bits read back as 0x4
Description
Read undefined
These bits read back as
0x00
3-21