Table 3-14 Ipcmcfgstat Register Bit Assignments; Figure 3-7 Ipcmcfgstat Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

3.3.14 Peripheral Identification Registers
ARM DDI 0306B
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31
Undefined
Table 3-14 lists the register bit assignments.
Bit
[31:22]
[21:16]
[15:14]
[13:8]
[7:3]
[2:0]
The IPCMPeriphID0-3 Registers are four 8-bit registers, that span address locations
. You can conceptually treat the registers as a single 32-bit register. The
0xFE0-0xFEC
read-only registers provide the following options of the peripheral:
PartNumber[11:0] This is used to identify the peripheral. The product code
DesignerID[19:12] This is the identification of the designer. ARM Limited is
Revision[23:20]
Configuration[31:24]
Figure 3-8 on page 3-20 shows the register bit assignments.
Copyright © 2003, 2004. ARM Limited. All rights reserved.
22 21 16 15 14 13
Mailboxes
Undefined

Figure 3-7 IPCMCFGSTAT Register bit assignments

Table 3-14 IPCMCFGSTAT Register bit assignments

Name Function
- Read undefined
Mailboxes Returns the value of the MBOXNUM input pins
- Read undefined
Interrupts Returns the value of the INTNUM input pins
- Read undefined
Data Words Returns the value of the DATANUM input pins
used for the IPCM.
(ASCII A).
This is the revision number of the peripheral. The revision number
starts from 0 and is revision dependent.
This is the configuration option of the peripheral. The
configuration value is 0.
Programmer's Model
8 7 3 2
Interrupts Undefined
0
Data
Words
is
0x320
0x41
3-19