ARM PrimeCelL PL320 Technical Reference Manual page 44

Functional Overview
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In this example, the following sequence occurs:
1. Core0 gains control of Mailbox0 and sets bit 0 in the IPCM0SOURCE Register.
2. Core0 gains control of Mailbox1 and sets bit 0 in the IPCM1SOURCE Register.
3. Core0 links Mailbox0 to Mailbox1 by setting bit 1 in the IPCM0MODE Register.
4. Core0 enables interrupts to Core0 and Core1 by setting bits 0 and 1 in the
IPCM0MSTATUS Register.
5. Core0 defines the destination core of Mailbox0 by setting bit 1 in the
IPCM0DSTATUS Register.
6. Core0 programs the data payload of Mailbox0 by setting the IPCM0DR0 Register
to .
DA7A0000
7. Core0 enables interrupts to Core0 and Core1 by setting bits 0 and 1 in the
IPCM1MSTATUS Register.
8. Core0 defines the destination core of Mailbox1 by setting bit 1 in the
IPCM1DSTATUS Register.
9. Core0 programs the data payload of Mailbox1 by setting Data1 to
10. Core0 sets bit 1 in the IPCM0SEND Register to send the message in Mailbox0.
11. Core1 reads the IPCMRIS1 Register and reads the data payload in Mailbox0.
12. Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to provide the
Manual Acknowledge back to Core0.
Note
There is no acknowledge interrupt to Core0.
13. The message in Mailbox1 is automatically sent, triggered by bit 1 in the
IPCM0SEND Register going HIGH and Auto Link mode being active.
14. Core1 reads the IPCMRIS1 Register and reads the data payload in Mailbox1.
15. Core1 clears bit 0 and sets bit 1 in the IPCM1SEND Register to provide the
Manual Acknowledge back to Core0.
Note
This sends the acknowledge interrupt to Core0.
Copyright © 2003, 2004. ARM Limited. All rights reserved.
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DA7A1111
ARM DDI 0306B