Table 3-4 Ipcmxdclear Register Bit Assignments; Table 3-5 Ipcmxdstatus Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

3.3.3 Mailbox Destination Clear Registers
3.3.4 Mailbox Destination Status Registers
3.3.5 Mailbox Mode Registers
ARM DDI 0306B
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The write-only IPCMxDCLEAR Registers clear bits in the Mailbox Destination
Registers. They can only be written to after the Mailbox Source Register is defined.
Table 3-4 lists the register bit assignments.
Bit Name
[31:0] Destination Clear
The read-only IPCMxDSTATUS Registers contain the current status of the Mailbox
Destination Registers.
When set, the Mailbox Destination Registers determine which cores to send the
message to through bit-wise encoding using the Channel ID for each core. For cores that
use multiple Channel IDs, only a single Channel ID is used per message.
The Mailbox Destination Registers are cleared in Auto Acknowledge Mode by
destination cores to clear the mailbox interrupts to each core. When not in Auto
Acknowledge mode, the Mailbox Destination Registers are only cleared by the source
core when the mailbox is being reassigned. The Mailbox Destination Registers are
cleared automatically by the mailbox regardless of which mode it is in when the
Mailbox Source Register is cleared.
Table 3-5 lists the register bit assignments.
Bit Name
[31:0] Destination Status
The read/write IPCMxMODE Registers define how the mailbox is used. The registers
can only be written to when the mailbox is assigned, indicated by a bit in the Mailbox
Source Register being set.
Copyright © 2003, 2004. ARM Limited. All rights reserved.

Table 3-4 IPCMxDCLEAR Register bit assignments

Function
Used to clear bits in the Mailbox Destination
Registers

Table 3-5 IPCMxDSTATUS Register bit assignments

Function
Gives the status of the Mailbox Destination Register.
Defines which interrupt output to assert for the message.
Programmer's Model
3-13