Table 3-19 Ipcmpcellid0 Register Bit Assignments; Figure 3-9 Primecell Identification Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

Programmer's Model
3.3.15 PrimeCell Identification Registers
Actual register bit assignment
Conceptual register bit assignment
3-22
Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from
The IPCMPCellID0-3 Registers are four 8-bit registers, that span address locations
. You can conceptually treat the registers as a single 32-bit register. The
0xFF0-0xFFC
register is used as a standard cross-peripheral identification system.
Figure 3-9 shows the register bit assignments.
IPCMPCellID3
7
31
IPCMPCellID3

Figure 3-9 PrimeCell Identification Register bit assignments

The four PrimeCell Identification Registers are described in the following subsections:
• PrimeCell Identification Register 0
• PrimeCell Identification Register 1 on page 3-23
• PrimeCell Identification Register 2 on page 3-23
• PrimeCell Identification Register 3 on page 3-23.
PrimeCell Identification Register 0
The hard-coded IPCMPCellID0 Register defines the reset value. Table 3-19 lists the bit
assignments for the IPCMPCellID0 Register.
Copyright © 2003, 2004. ARM Limited. All rights reserved.
IPCMPCellID2 IPCMPCellID1
0 7 0 7
24 23 16 15
IPCMPCellID2 IPCMPCellID1

Table 3-19 IPCMPCellID0 Register bit assignments

Bits Name
[31:8] -
[7:0] IPCMPCellID0
IPCMPCellID0
0 7 0
8 7 0
IPCMPCellID0
Description
Read undefined
These bits read back as 0x0D
ARM DDI 0306B