Figure 2-9 Configuration, Messaging From Core0 To Cores 1, 2, And 3 Using Auto Acknowledge - ARM PrimeCelL PL320 Technical Reference Manual

Functional Overview
2.3.3 Messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge
A HB bus

Figure 2-9 Configuration, messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge

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12. Core1 reads the IPCMRIS1 Register and reads the data payload.
13. Core1 optionally updates the data payload for the Acknowledge,
14. Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to provide the
Manual Acknowledge back to Core0.
15. Core0 reads the IPCMRIS0 Register and reads the data payload.
16. Core0 clears the interrupt and releases ownership of the mailbox by clearing the
IPCM0SOURCE Register, which in turn clears the IPCM0DSTATUS,
IPCM0MSTATUS, IPCM0SEND, and IPCM0DR0 Registers.
In this example system, there are four cores and four mailboxes:
• Core0 uses Channel ID1
• Core1 uses Channel ID2
• Core2 uses Channel ID4
• Core3 uses Channel ID8.
Core0 is the source core and sends a message to three destination cores, 1, 2, and 3. This
example assumes that the IPCM is not in integration test mode. Mailboxes 1-3 are
inactive and Auto Link is disabled. Figure 2-9 shows the configuration.
IPCM INT[0] IPCM INT[1]
Interrupt Interrupt
controller0 controller1
Core0 Core1
Figure 2-10 on page 2-23 shows the messaging sequence.
Copyright © 2003, 2004. ARM Limited. All rights reserved.
IPCM INT[2] IPCM INT[3]
Interrupt Interrupt
controller2 controller3
Core2 Core3
.
DA7A3333
IPCM
Minimum
conf iguration:
M BOXNUM =1
INTNUM =4
DATANUM =1
ARM DDI 0306B