Table 3-9 Ipcmxmstatus Register Bit Assignments; Figure 3-5 Ipcmxsend Register Bit Assignments - ARM PrimeCelL PL320 Technical Reference Manual

Programmer's Model
3.3.9 Mailbox Send Registers
3-16
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Table 3-9 lists the register bit assignments.
Bit
[31:0]
The read/write IPCMxSEND Registers send the message to either the source or
destination cores.
The Mailbox Send Register bits can only be written to after the Mailbox Source Register
is defined:
• setting bit 0 generates an interrupt to the destination core(s)
• setting bit 1 generates an interrupt to the source core.
Note
Setting both bits 0 and 1 is not valid and can give unpredictable results. Clearing any
send bit clears the interrupt generated by that mailbox.
In Auto Acknowledge mode, when the Mailbox Destination Status Register changes
from being non-zero to zero and the Mailbox Send Register currently contains 01, the
mailbox automatically changes the register to 10, triggering the Auto Acknowledge
interrupt back to the source core.
The Mailbox Send Registers are cleared when the Mailbox Source Register is cleared.
Figure 3-5 shows the register bit assignments.
31
Copyright © 2003, 2004. ARM Limited. All rights reserved.

Table 3-9 IPCMxMSTATUS Register bit assignments

Name Function
Mask Status Gives the status of the Mailbox Mask Registers.
For each bit position:
1 = Mailbox interrupt enabled
0 = Mailbox interrupt disabled, polling used instead.
Undefined

Figure 3-5 IPCMxSEND Register bit assignments

2 1 0
Send
ARM DDI 0306B