About The Ipcm - ARM PrimeCelL PL320 Technical Reference Manual

Inter-processor communications module

Hide thumbs

Table Of Contents

Table of Contents

Introduction

1.1

About the IPCM

1-2

Arrow.com.

Downloaded from

The IPCM provides up to 32 mailboxes with control logic and interrupt generation to

support inter-processor communication. An AHB interface enables access from source

and destination cores.

The IPCM:

•

sends interrupts to other cores

•

passes small amounts of data to other cores.

The mailboxes within the IPCM can be available as floating resources between cores or

as dedicated resources to specific cores. A source core can have multiple mailboxes and

send messages in parallel.

The IPCM consists of the following:

•

1-32 programmable mailboxes, each comprising:

—

a single 1-32-bit Mailbox Source Register

—

a single 1-32-bit Mailbox Destination Register with separate Set, Clear, and

Status addresses

—

a single 2-bit Mailbox Mode Register to enable Auto Acknowledge and

Auto Link modes

—

a single 1-32-bit Mailbox Mask Register with separate Set, Clear, and

Status addresses to enable you to mask out individual mailbox interrupts for

cores requiring to poll rather than be interrupted

—

a single 2-bit Mailbox Send Register to trigger mailbox interrupts to source

and destination cores

—

0-7 32-bit data registers to store the message.

•

1-32 sets of read-only interrupt status registers, one for each interrupt, each

comprising:

—

1-32-bit Raw Interrupt Status Register (each bit corresponds to each

mailbox)

—

1-32-bit Masked Interrupt Status Register (each bit corresponds to each

mailbox).

•

A 32-bit Configuration Status Register

•

Integration Test Registers for the interrupt outputs

•

Peripheral and PrimeCell Identification Registers.

ARM DDI 0306B

Table of Contents

About The Ipcm - ARM PrimeCelL PL320 Technical Reference Manual

About the IPCM

Related Manuals for ARM PrimeCelL PL320

Related Content for ARM PrimeCelL PL320

Table of Contents