ARM PrimeCelL PL320 Technical Reference Manual page 54

Programmer's Model
Name
-
-
-
-
-
-
-
-
-
-
-
-
-
IPCMMIS0
IPCMRIS0
-
3-8
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Base Reset
Type
offset value
0x4C0-0x4 - -
FC
0x500-0x5 - -
3C
0x540-0x5 - -
7C
0x580-0x5 - -
BC
0x5C0-0x5 - -
FC
0x600-0x6 - -
3C
0x640-0x6 - -
7C
0x680-0x6 - -
BC
0x6C0-0x6 - -
FC
0x700-0x7 - -
3C
0x740-0x7 - -
7C
0x780-0x7 - -
BC
0x7C0-0x7 - -
FC
0x800 RO 0x00000000
RO
0x804 0x00000000
0x808-0x8 - -
0C
Copyright © 2003, 2004. ARM Limited. All rights reserved.
Table 3-1 IPCM register summary (continued)
Description
Reserved for Mailbox19
Reserved for Mailbox20
Reserved for Mailbox21
Reserved for Mailbox22
Reserved for Mailbox23
Reserved for Mailbox24
Reserved for Mailbox25
Reserved for Mailbox26
Reserved for Mailbox27
Reserved for Mailbox28
Reserved for Mailbox29
Reserved for Mailbox30
Reserved for Mailbox31
See Masked Interrupt Status Registers on page 3-17
See Raw Interrupt Status Registers on page 3-18
Reserved for Interrupt1
ARM DDI 0306B