Figure 2-6 Messaging From Core0 To Core1 - ARM PrimeCelL PL320 Technical Reference Manual

Inter-processor communications module

Hide thumbs

Table Of Contents

Table of Contents

IPCM0SOURCE[1:0]

IPCM0DSTATUS[1:0]

IPCM0MSTATUS[1:0]

IPCM0SEND[1:0]

IPCM0DR0[31:0]

IPCMRIS0[3:0]

IPCMRIS1[3:0]

ARM DDI 0306B

Arrow.com.

Downloaded from

IPCM0MODE

00000000

IPCMINT[3:0]

In this example, the following sequence occurs:

Core0 gains control of Mailbox0 and identifies itself as the source core by setting

bit 0 in the IPCM0SOURCE Register.

Core0 enables interrupts to Core0 and Core1 by setting bits 0 and 1 in the

IPCM0MSTATUS Register.

Core0 defines the destination core by setting bit 1 in the IPCM0DSTATUS

Core0 programs the data payload,

Core0 sets Mailbox Send Register bit 0 to trigger the Mailbox0 interrupt to Core1.

Core1 reads the IPCMRIS1 Register to determine which mailbox caused the

interrupt. In this case, only Mailbox0 is indicated.

Core1 reads the data payload.

Core1 optionally updates the data payload with the Acknowledge data,

Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to clear its interrupt

and provide the Manual Acknowledge interrupt back to Core0.

10.

Core0 reads the IPCMRIS0 Register to determine which mailbox caused the

interrupt. Again, only Mailbox0 is indicated.

11.

Core0 reads the Acknowledge payload data.

DA7A0000

DA7A1111