ARM PrimeCelL PL320 Technical Reference Manual page 84

Index
IPCMPCellD3 Register 3-23
IPCMPeriphID0 Register 3-20
IPCMPeriphID0-3 Registers 3-19
IPCMPeriphID1 Register 3-21
IPCMPeriphID2 Register 3-21
IPCMPeriphID3 Register 3-21
IPCMRISx Registers 3-18
IPCMTCR Register 4-3
IPCMTOR Register 4-3
IPCMxDCLEAR Registers 3-13
IPCMxDR0-6 Registers 3-17
IPCMxDSET Registers 3-12
IPCMxDSTATUS Registers 3-13
IPCMxMCLEAR Registers 3-15
IPCMxMODE Registers 3-13
IPCMxMSET Registers 3-14
IPCMxMSTATUS Registers 3-15
IPCMxSEND Registers 3-16
IPCMxSOURCE Registers 3-12
M
Mailboxes 2-2
Auto Acknowledge mode 2-9
Auto Link mode 2-10
configuration status 2-12
data 2-9
destination core 2-8
interrupts 2-10
mask 2-8
mode 2-9
send 2-9
source core 2-8
usage constraints 2-16
MBOXNUM A-3
Messaging
back-to-back 2-20
Core0 to Core1 2-18
using Auto Acknowledge 2-22
using Auto Link 2-24
N
Numerical conventions xiii
Index-2
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O
Operation 2-4
Overview 1-2
P
Product revision status x
Programmer's model 3-2
R
Register descriptions 3-12
Registers
IPCMCFGSTAT 3-18
IPCMMISx 3-17
IPCMPCellID0 3-22
IPCMPCellID0-3 3-22
IPCMPCellID1 3-23
IPCMPCellID2 3-23
IPCMPCellID3 3-23
IPCMPeriphID0 3-20
IPCMPeriphID0-3 3-19
IPCMPeriphID1 3-21
IPCMPeriphID2 3-21
IPCMPeriphID3 3-21
IPCMRISx 3-18
IPCMTCR 4-3
IPCMTOR 4-3
IPCMxDCLEAR 3-13
IPCMxDR0-6 3-17
IPCMxDSET 3-12
IPCMxDSTATUS 3-13
IPCMxMCLEAR 3-15
IPCMxMODE 3-13
IPCMxMSET 3-14
IPCMxMSTATUS 3-15
IPCMxSEND 3-16
IPCMxSOURCE 3-12
Revision
status x
S
Scan test signals A-3
Scan testing 4-2
Copyright © 2003, 2004. ARM Limited. All rights reserved.
SCANENABLE A-3
SCANINHCLK A-3
SCANOUTHCLK A-3
Signal descriptions A-1
Signal naming conventions xii
System diagram 2-3
T
Test registers 4-3
Timing diagram conventions xi
Typographical conventions xi
ARM DDI 0306B