ARM PrimeCelL PL320 Technical Reference Manual page 42

Inter-processor communications module

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Functional Overview

2.3.4

Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1

2-24

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11.

Core2 reads the IPCMRIS2 Register and reads the data payload.

12.

Core2 clears bit 2 in the IPCM0DSTATUS Register. As the final Mailbox

Destination Register bit is cleared, the mailbox automatically detects this, clears

Mailbox Send Register bit 0 and sets Mailbox Send Register bit 1 to provide the

Auto Acknowledge back to the source core, Core0. The data registers are not

updated in Auto Acknowledge mode.

13.

Core0 reads Status0 and reads the data payload.

14.

Core0 clears the interrupt and releases ownership of the mailbox by clearing the

IPCM0SOURCE register, which in turn clears the IPCM0SEND and IPCM0DR0

Registers.

Note

If Core0 has another message to send, it can maintain ownership of the mailbox by

keeping the IPCM0SOURCE Register set, and updating the IPCM0DSTATUS,

IPCM0MODE, IPCM0MSTATUS, and IPCM0DR0 Registers with the new message at

step 14.

In this example system, there are two cores and four mailboxes. Core0 is the source core

and Core1 is the destination core. Core0 uses Channel ID1 and Core1 uses Channel

ID2. Core0 sets up Mailbox0 and Mailbox1 in Auto Link mode, and sends a message

to Core1. Core1 responds to each interrupt separately and acknowledges both. Core0

only obtains an acknowledge interrupt when Core1 has finished with the final message.

This example assumes that the IPCM has interrupts enabled and is not in integration test

mode. Mailboxes 2-3 are inactive and Auto Acknowledge is disabled. Figure 2-11 on

page 2-25 shows the configuration.

ARM DDI 0306B

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